tcxmaster.c

Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序

#pragma NOIV                    // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
//   File:      tcxmaster.c
//   Contents:  Hooks required to implement USB peripheral function.
//              Code written for FX2 56-pin REVD...
//              This firmware is used to test the FX ext. master CY3682 DK
//   Copyright (c) 2001 Cypress Semiconductor All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h"            // SYNCDELAY macro

extern BOOL GotSUD;             // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;

BYTE Configuration;             // Current configuration
BYTE AlternateSetting;          // Alternate settings
/*
// EZUSB FX2 PORTA = slave fifo enable(s), when IFCFG[1:0]=11
sbit PA0 = IOA ^ 0;             // alt. func., INT0#
sbit PA1 = IOA ^ 1;             // alt. func., INT1#
sbit PA2 = IOA ^ 2;          // is SLOE
sbit PA3 = IOA ^ 3;             // alt. func., WU2
sbit PA4 = IOA ^ 4;          // is FIFOADR0
sbit PA5 = IOA ^ 5;          // is FIFOADR1
sbit PA6 = IOA ^ 6;          // is PKTEND
sbit PA7 = IOA ^ 7;          // is FLAGD

// EZUSB FX2 PORTC i/o...       port NA for 56-pin FX2
sbit PC0 = IOC ^ 0;
sbit PC1 = IOC ^ 1;
sbit PC2 = IOC ^ 2;
sbit PC3 = IOC ^ 3;
sbit PC4 = IOC ^ 4;
sbit PC5 = IOC ^ 5;
sbit PC6 = IOC ^ 6;
sbit PC7 = IOC ^ 7;

// EZUSB FX2 PORTB = FD[7:0], when IFCFG[1:0]=11
sbit PB0 = IOB ^ 0;
sbit PB1 = IOB ^ 1;
sbit PB2 = IOB ^ 2;
sbit PB3 = IOB ^ 3;
sbit PB4 = IOB ^ 4;
sbit PB5 = IOB ^ 5;
sbit PB6 = IOB ^ 6;
sbit PB7 = IOB ^ 7;

// EZUSB FX2 PORTD = FD[15:8], when IFCFG[1:0]=11 and WORDWIDE=1
sbit PD0 = IOD ^ 0;
sbit PD1 = IOD ^ 1;
sbit PD2 = IOD ^ 2;
sbit PD3 = IOD ^ 3;
sbit PD4 = IOD ^ 4;
sbit PD5 = IOD ^ 5;
sbit PD6 = IOD ^ 6;
sbit PD7 = IOD ^ 7;

*/
void TD_Init(void)    // Called once at startup
{
 REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1


 SYNCDELAY; 
// this defines the external interface to be the following:
 IFCONFIG = 0x43;//0x43; 			
//			operate synchronously
// 			use IFCLK pin driven by external logic (5MHz to 48MHz)
// 			use slave FIFO interface pins driven sync by external master
// 0100 0011
// Bit		Value	Register 	Function
// bit.7	0		This bit selects the clock source for both the FIFOS and GPIF. 
//    If IFCLKSRC=0, the external clock on the IFCLK pin is selected. 
//    If IFCLKSRC=1 (default), an internal 30- or 48-MHz (default) clock is used.
// bit.6	0		This bit selects the internal FIFO & GPIF clock frequency.
// bit.5	0		IFCLK pin output enable
// bit.4	0		This bit indicates that the IFCLK signal is inverted.
// bit.3    0       FIFO/GPIF Asynchronous Mode
//  ASYNC=0, the FIFO/GPIF operate synchronously a clock is supplied either internally or externally on the IFCLK pin;
//  ASYNC=1, the FIFO/GPIF operate asynchronously: no clock signal input to IFCLK is required;
// bit.2	0		Drive GSTATE [2:0] on PORTE [2:0]
// bit.10	11		Select Interface Mode (Ports, GPIF, or Slave FIFO)
//				IFCFG1 IFCFG0 Configuration
//				0 	0 Ports
//				0 	1 Reserved
//				1 	0 GPIF Interface (internal master)
//				1 	1 Slave FIFO Interface (external master)

 EP2FIFOCFG = 0x09; 		// this lets the FX2 auto commit IN packets, gives the
 SYNCDELAY;
 EP2CFG = 0xE0; 			//EP2 ,IN,BULK,512BYTE, x4 buffer

 PINFLAGSAB = 0x00; 		// defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]
 SYNCDELAY; 				// FLAGB as full flag, as pointed to by FIFOADR[1:0]
 PINFLAGSCD = 0x00; 		// FLAGC as empty flag, as pointed to by FIFOADR[1:0]
 PORTACFG = 0x40; 			// used PA7/FLAGD as a port pin, not as a FIFO flag
 FIFOPINPOLAR = 0x00; 		// set all slave FIFO interface pins as active low

 SYNCDELAY;
 EP2AUTOINLENH = 0x02; 		// you can define these as you wish,
 SYNCDELAY; 				// to have the FX2 automatically limit IN's
 EP2AUTOINLENL = 0x00;

 SYNCDELAY;
 EP4CFG = 0x00;
 SYNCDELAY;
 EP6CFG = 0x00;
 SYNCDELAY;
 EP8CFG = 0x00;

 SYNCDELAY;
 FIFORESET = 0x80; // reset all FIFOs
 SYNCDELAY;
 FIFORESET = 0x02;
 SYNCDELAY;
 FIFORESET = 0x04;
 SYNCDELAY;
 FIFORESET = 0x06;
 SYNCDELAY;
 FIFORESET = 0x08;
 SYNCDELAY;
 FIFORESET = 0x00;

// ability to send zero length packets,
 // and sets the slave FIFO data interface to 16-bits
// EP8CFG = 0xE0; 			// sets EP8 valid for IN's
 // and defines the endpoint for 512 byte packets, 2x buffered

	// won't generally need FLAGD
 SYNCDELAY;
 EP2FIFOPFH = 0x82; 		// you can define the programmable flag (FLAGA)
}

void TD_Poll( void )
{ // Called repeatedly while the device is idle
//	IOC = 0x00;
//	EZUSB_Delay(1000);
//	IOC = 0xff;
//   EZUSB_Delay(1000);
  // ...nothing to do... slave fifo's are in AUTO mode...

}

BOOL TD_Suspend( void )          
{ // Called before the device goes into suspend mode
   return( TRUE );
}

BOOL TD_Resume( void )          
{ // Called after the device resumes
   return( TRUE );
}

//-----------------------------------------------------------------------------
// Device Request hooks
//   The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor( void )
{
   return( TRUE );
}

BOOL DR_SetConfiguration( void )   
{ // Called when a Set Configuration command is received
  
  if( EZUSB_HIGHSPEED( ) )
  { // ...FX2 in high speed mode
    EP2AUTOINLENH = 0x02;

    SYNCDELAY;
    EP2AUTOINLENL = 0x00;

  }
  else
  { // ...FX2 in full speed mode
    EP2AUTOINLENH = 0x00;
    SYNCDELAY;
    EP2AUTOINLENL = 0x40;
    SYNCDELAY;
  }
      
  Configuration = SETUPDAT[ 2 ];
  return( TRUE );        // Handled by user code
}

BOOL DR_GetConfiguration(void)   // Called when a Get Configuration command is received
{
   if( EZUSB_HIGHSPEED( ) )
   {
  EP2AUTOINLENH = 0x02;  // auto in length is 0x0400 = 1024
  SYNCDELAY;
  EP2AUTOINLENL = 0x00;
   }
   else
   { 
  EP2AUTOINLENH = 0x00;  // auto in length is 0x0040 = 64
  SYNCDELAY;
  EP2AUTOINLENL = 0x40;
   }

   EP0BUF[0] = Configuration;
   EP0BCH = 0;
   EP0BCL = 1;
   return(TRUE);              // Handled by user code
}


BOOL DR_SetInterface( void )       
{ // Called when a Set Interface command is received
   AlternateSetting = SETUPDAT[ 2 ];
   return( TRUE );        // Handled by user code
}

BOOL DR_GetInterface( void )       
{ // Called when a Set Interface command is received
   EP0BUF[ 0 ] = AlternateSetting;
   EP0BCH = 0;
   EP0BCL = 1;
   return( TRUE );        // Handled by user code
}

BOOL DR_GetStatus( void )
{
   return( TRUE );
}

BOOL DR_ClearFeature( void )
{
   return( TRUE );
}

BOOL DR_SetFeature( void )
{
   return( TRUE );
}

BOOL DR_VendorCmnd( void )
{
  return( TRUE );
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav( void ) interrupt 0
{
   GotSUD = TRUE;         // Set flag
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUDAV;      // Clear SUDAV IRQ
}

// Setup Token Interrupt Handler
void ISR_Sutok( void ) interrupt 0
{
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUTOK;      // Clear SUTOK IRQ
}

void ISR_Sof( void ) interrupt 0
{
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSOF;        // Clear SOF IRQ
}

void ISR_Ures( void ) interrupt 0
{
   if ( EZUSB_HIGHSPEED( ) )
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }
   
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmURES;       // Clear URES IRQ
}

void ISR_Susp( void ) interrupt 0
{
   Sleep = TRUE;
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUSP;
}

void ISR_Highspeed( void ) interrupt 0
{
   if ( EZUSB_HIGHSPEED( ) )
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }

   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack( void ) interrupt 0
{
}
void ISR_Stub( void ) interrupt 0
{
}
void ISR_Ep0in( void ) interrupt 0
{
}
void ISR_Ep0out( void ) interrupt 0
{
}
void ISR_Ep1in( void ) interrupt 0
{
}
void ISR_Ep1out( void ) interrupt 0
{
}
void ISR_Ep2inout( void ) interrupt 0
{
}
void ISR_Ep4inout( void ) interrupt 0
{
}
void ISR_Ep6inout( void ) interrupt 0
{
}
void ISR_Ep8inout( void ) interrupt 0
{
}
void ISR_Ibn( void ) interrupt 0
{
}
void ISR_Ep0pingnak( void ) interrupt 0
{
}
void ISR_Ep1pingnak( void ) interrupt 0
{
}
void ISR_Ep2pingnak( void ) interrupt 0
{
}
void ISR_Ep4pingnak( void ) interrupt 0
{
}
void ISR_Ep6pingnak( void ) interrupt 0
{
}
void ISR_Ep8pingnak( void ) interrupt 0
{
}
void ISR_Errorlimit( void ) interrupt 0
{
}
void ISR_Ep2piderror( void ) interrupt 0
{
}
void ISR_Ep4piderror( void ) interrupt 0
{
}
void ISR_Ep6piderror( void ) interrupt 0
{
}
void ISR_Ep8piderror( void ) interrupt 0
{
}
void ISR_Ep2pflag( void ) interrupt 0
{
}
void ISR_Ep4pflag( void ) interrupt 0
{
}
void ISR_Ep6pflag( void ) interrupt 0
{
}
void ISR_Ep8pflag( void ) interrupt 0
{
}
void ISR_Ep2eflag( void ) interrupt 0
{
}
void ISR_Ep4eflag( void ) interrupt 0
{
}
void ISR_Ep6eflag( void ) interrupt 0
{
}
void ISR_Ep8eflag( void ) interrupt 0
{
}
void ISR_Ep2fflag( void ) interrupt 0
{
}
void ISR_Ep4fflag( void ) interrupt 0
{
}
void ISR_Ep6fflag( void ) interrupt 0
{
}
void ISR_Ep8fflag( void ) interrupt 0
{
}
void ISR_GpifComplete( void ) interrupt 0
{
}
void ISR_GpifWaveform( void ) interrupt 0
{
}