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📄 tcxmaster.lst

📁 Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序
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C51 COMPILER V7.50   TCXMASTER                     08/04/2008 21:19:38 PAGE 1   


C51 COMPILER V7.50, COMPILATION OF MODULE TCXMASTER
OBJECT MODULE PLACED IN tcxmaster.OBJ
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE tcxmaster.c OPTIMIZE(6,SPEED) MODDP
                    -2 DEBUG OBJECTEXTEND CODE SYMBOLS PAGEWIDTH(80)

line level    source

   1          #pragma NOIV                    // Do not generate interrupt vecto
             -rs
   2          //----------------------------------------------------------------
             --------------
   3          //   File:      tcxmaster.c
   4          //   Contents:  Hooks required to implement USB peripheral functio
             -n.
   5          //              Code written for FX2 56-pin REVD...
   6          //              This firmware is used to test the FX ext. master C
             -Y3682 DK
   7          //   Copyright (c) 2001 Cypress Semiconductor All rights reserved
   8          //----------------------------------------------------------------
             --------------
   9          #include "fx2.h"
  10          #include "fx2regs.h"
  11          #include "fx2sdly.h"            // SYNCDELAY macro
  12          
  13          extern BOOL GotSUD;             // Received setup data flag
  14          extern BOOL Sleep;
  15          extern BOOL Rwuen;
  16          extern BOOL Selfpwr;
  17          
  18          BYTE Configuration;             // Current configuration
  19          BYTE AlternateSetting;          // Alternate settings
  20          /*
  21          // EZUSB FX2 PORTA = slave fifo enable(s), when IFCFG[1:0]=11
  22          sbit PA0 = IOA ^ 0;             // alt. func., INT0#
  23          sbit PA1 = IOA ^ 1;             // alt. func., INT1#
  24          sbit PA2 = IOA ^ 2;          // is SLOE
  25          sbit PA3 = IOA ^ 3;             // alt. func., WU2
  26          sbit PA4 = IOA ^ 4;          // is FIFOADR0
  27          sbit PA5 = IOA ^ 5;          // is FIFOADR1
  28          sbit PA6 = IOA ^ 6;          // is PKTEND
  29          sbit PA7 = IOA ^ 7;          // is FLAGD
  30          
  31          // EZUSB FX2 PORTC i/o...       port NA for 56-pin FX2
  32          sbit PC0 = IOC ^ 0;
  33          sbit PC1 = IOC ^ 1;
  34          sbit PC2 = IOC ^ 2;
  35          sbit PC3 = IOC ^ 3;
  36          sbit PC4 = IOC ^ 4;
  37          sbit PC5 = IOC ^ 5;
  38          sbit PC6 = IOC ^ 6;
  39          sbit PC7 = IOC ^ 7;
  40          
  41          // EZUSB FX2 PORTB = FD[7:0], when IFCFG[1:0]=11
  42          sbit PB0 = IOB ^ 0;
  43          sbit PB1 = IOB ^ 1;
  44          sbit PB2 = IOB ^ 2;
  45          sbit PB3 = IOB ^ 3;
  46          sbit PB4 = IOB ^ 4;
  47          sbit PB5 = IOB ^ 5;
  48          sbit PB6 = IOB ^ 6;
  49          sbit PB7 = IOB ^ 7;
C51 COMPILER V7.50   TCXMASTER                     08/04/2008 21:19:38 PAGE 2   

  50          
  51          // EZUSB FX2 PORTD = FD[15:8], when IFCFG[1:0]=11 and WORDWIDE=1
  52          sbit PD0 = IOD ^ 0;
  53          sbit PD1 = IOD ^ 1;
  54          sbit PD2 = IOD ^ 2;
  55          sbit PD3 = IOD ^ 3;
  56          sbit PD4 = IOD ^ 4;
  57          sbit PD5 = IOD ^ 5;
  58          sbit PD6 = IOD ^ 6;
  59          sbit PD7 = IOD ^ 7;
  60          
  61          */
  62          void TD_Init(void)    // Called once at startup
  63          {
  64   1       REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1
  65   1      
  66   1      
  67   1       SYNCDELAY; 
  68   1      // this defines the external interface to be the following:
  69   1       IFCONFIG = 0x43;//0x43;                        
  70   1      //                      operate synchronously
  71   1      //                      use IFCLK pin driven by external logic (5MHz to 48MHz)
  72   1      //                      use slave FIFO interface pins driven sync by external master
  73   1      // 0100 0011
  74   1      // Bit          Value   Register        Function
  75   1      // bit.7        0               This bit selects the clock source for both the FIFOS a
             -nd GPIF. 
  76   1      //    If IFCLKSRC=0, the external clock on the IFCLK pin is select
             -ed. 
  77   1      //    If IFCLKSRC=1 (default), an internal 30- or 48-MHz (default)
             - clock is used.
  78   1      // bit.6        0               This bit selects the internal FIFO & GPIF clock freque
             -ncy.
  79   1      // bit.5        0               IFCLK pin output enable
  80   1      // bit.4        0               This bit indicates that the IFCLK signal is inverted.
  81   1      // bit.3    0       FIFO/GPIF Asynchronous Mode
  82   1      //  ASYNC=0, the FIFO/GPIF operate synchronously a clock is suppli
             -ed either internally or externally on the IFCLK pin;
  83   1      //  ASYNC=1, the FIFO/GPIF operate asynchronously: no clock signal
             - input to IFCLK is required;
  84   1      // bit.2        0               Drive GSTATE [2:0] on PORTE [2:0]
  85   1      // bit.10       11              Select Interface Mode (Ports, GPIF, or Slave FIFO)
  86   1      //                              IFCFG1 IFCFG0 Configuration
  87   1      //                              0       0 Ports
  88   1      //                              0       1 Reserved
  89   1      //                              1       0 GPIF Interface (internal master)
  90   1      //                              1       1 Slave FIFO Interface (external master)
  91   1      
  92   1       EP2FIFOCFG = 0x09;             // this lets the FX2 auto commit IN packets,
             - gives the
  93   1       SYNCDELAY;
  94   1       EP2CFG = 0xE0;                         //EP2 ,IN,BULK,512BYTE, x4 buffer
  95   1      
  96   1       PINFLAGSAB = 0x00;             // defines FLAGA as prog-level flag, pointed
             - to by FIFOADR[1:0]
  97   1       SYNCDELAY;                             // FLAGB as full flag, as pointed to by FIFOADR[1:
             -0]
  98   1       PINFLAGSCD = 0x00;             // FLAGC as empty flag, as pointed to by FIF
             -OADR[1:0]
  99   1       PORTACFG = 0x40;                       // used PA7/FLAGD as a port pin, not as a FIF
             -O flag
 100   1       FIFOPINPOLAR = 0x00;           // set all slave FIFO interface pins as ac
C51 COMPILER V7.50   TCXMASTER                     08/04/2008 21:19:38 PAGE 3   

             -tive low
 101   1      
 102   1       SYNCDELAY;
 103   1       EP2AUTOINLENH = 0x02;          // you can define these as you wish,
 104   1       SYNCDELAY;                             // to have the FX2 automatically limit IN's
 105   1       EP2AUTOINLENL = 0x00;
 106   1      
 107   1       SYNCDELAY;
 108   1       EP4CFG = 0x00;
 109   1       SYNCDELAY;
 110   1       EP6CFG = 0x00;
 111   1       SYNCDELAY;
 112   1       EP8CFG = 0x00;
 113   1      
 114   1       SYNCDELAY;
 115   1       FIFORESET = 0x80; // reset all FIFOs
 116   1       SYNCDELAY;
 117   1       FIFORESET = 0x02;
 118   1       SYNCDELAY;
 119   1       FIFORESET = 0x04;
 120   1       SYNCDELAY;
 121   1       FIFORESET = 0x06;
 122   1       SYNCDELAY;
 123   1       FIFORESET = 0x08;
 124   1       SYNCDELAY;
 125   1       FIFORESET = 0x00;
 126   1      
 127   1      // ability to send zero length packets,
 128   1       // and sets the slave FIFO data interface to 16-bits
 129   1      // EP8CFG = 0xE0;                       // sets EP8 valid for IN's
 130   1       // and defines the endpoint for 512 byte packets, 2x buffered
 131   1      
 132   1              // won't generally need FLAGD
 133   1       SYNCDELAY;
 134   1       EP2FIFOPFH = 0x82;             // you can define the programmable flag (FLA
             -GA)
 135   1      }
 136          
 137          void TD_Poll( void )
 138          { // Called repeatedly while the device is idle
 139   1      //      IOC = 0x00;
 140   1      //      EZUSB_Delay(1000);
 141   1      //      IOC = 0xff;
 142   1      //   EZUSB_Delay(1000);
 143   1        // ...nothing to do... slave fifo's are in AUTO mode...
 144   1      
 145   1      }
 146          
 147          BOOL TD_Suspend( void )          
 148          { // Called before the device goes into suspend mode
 149   1         return( TRUE );
 150   1      }
 151          
 152          BOOL TD_Resume( void )          
 153          { // Called after the device resumes
 154   1         return( TRUE );
 155   1      }
 156          
 157          //----------------------------------------------------------------
             --------------
 158          // Device Request hooks
 159          //   The following hooks are called by the end point 0 device requ
C51 COMPILER V7.50   TCXMASTER                     08/04/2008 21:19:38 PAGE 4   

             -est parser.
 160          //----------------------------------------------------------------
             --------------
 161          BOOL DR_GetDescriptor( void )
 162          {
 163   1         return( TRUE );
 164   1      }
 165          
 166          BOOL DR_SetConfiguration( void )   
 167          { // Called when a Set Configuration command is received
 168   1        
 169   1        if( EZUSB_HIGHSPEED( ) )
 170   1        { // ...FX2 in high speed mode
 171   2          EP2AUTOINLENH = 0x02;
 172   2      
 173   2          SYNCDELAY;
 174   2          EP2AUTOINLENL = 0x00;
 175   2      
 176   2        }
 177   1        else
 178   1        { // ...FX2 in full speed mode
 179   2          EP2AUTOINLENH = 0x00;
 180   2          SYNCDELAY;
 181   2          EP2AUTOINLENL = 0x40;
 182   2          SYNCDELAY;
 183   2        }
 184   1            
 185   1        Configuration = SETUPDAT[ 2 ];
 186   1        return( TRUE );        // Handled by user code
 187   1      }
 188          
 189          BOOL DR_GetConfiguration(void)   // Called when a Get Configuratio
             -n command is received
 190          {
 191   1         if( EZUSB_HIGHSPEED( ) )
 192   1         {
 193   2        EP2AUTOINLENH = 0x02;  // auto in length is 0x0400 = 1024
 194   2        SYNCDELAY;
 195   2        EP2AUTOINLENL = 0x00;
 196   2         }
 197   1         else
 198   1         { 
 199   2        EP2AUTOINLENH = 0x00;  // auto in length is 0x0040 = 64
 200   2        SYNCDELAY;
 201   2        EP2AUTOINLENL = 0x40;
 202   2         }
 203   1      
 204   1         EP0BUF[0] = Configuration;
 205   1         EP0BCH = 0;
 206   1         EP0BCL = 1;
 207   1         return(TRUE);              // Handled by user code
 208   1      }
 209          
 210          
 211          BOOL DR_SetInterface( void )       
 212          { // Called when a Set Interface command is received
 213   1         AlternateSetting = SETUPDAT[ 2 ];
 214   1         return( TRUE );        // Handled by user code
 215   1      }
 216          
 217          BOOL DR_GetInterface( void )       
 218          { // Called when a Set Interface command is received
C51 COMPILER V7.50   TCXMASTER                     08/04/2008 21:19:38 PAGE 5   

 219   1         EP0BUF[ 0 ] = AlternateSetting;
 220   1         EP0BCH = 0;
 221   1         EP0BCL = 1;
 222   1         return( TRUE );        // Handled by user code
 223   1      }
 224          
 225          BOOL DR_GetStatus( void )
 226          {
 227   1         return( TRUE );
 228   1      }
 229          
 230          BOOL DR_ClearFeature( void )
 231          {
 232   1         return( TRUE );
 233   1      }
 234          
 235          BOOL DR_SetFeature( void )
 236          {
 237   1         return( TRUE );
 238   1      }
 239          
 240          BOOL DR_VendorCmnd( void )
 241          {
 242   1        return( TRUE );
 243   1      }
 244          
 245          //----------------------------------------------------------------
             --------------
 246          // USB Interrupt Handlers
 247          //   The following functions are called by the USB interrupt jump 

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