add8.vhd

组合电路的设计8位加法器设计(ADD8.vhd)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADD8 IS 
  PORT (A0,A1,A2,A3,A4,A5,A6,A7,B0,B1,B2,B3,B4,B5,B6,B7,C0 : IN STD_LOGIC;
         CONT,S0,S1,S2,S3,S4,S5,S6,S7 : OUT STD_LOGIC);  --AB is input ;s is sum;C0 SHI JIN WEI
END ENTITY ADD8;
ARCHITECTURE ADD8 OF ADD8 IS
 COMPONENT ADD2
  PORT (A,B,Cin : IN STD_LOGIC;
         CONT,S : OUT STD_LOGIC);
 END COMPONENT;
 SIGNAL D,E,F,G,H,I,J : STD_LOGIC;
BEGIN 
 L0: ADD2 PORT MAP(A=>A0,B=>B0,Cin=>C0,S=>S0,CONT=>D);
 L1: ADD2 PORT MAP(A=>A1,B=>B1,Cin=>D,S=>S1,CONT=>E);
 L2: ADD2 PORT MAP(A=>A2,B=>B2,Cin=>E,S=>S2,CONT=>F);
 L3: ADD2 PORT MAP(A=>A3,B=>B3,Cin=>F,S=>S3,CONT=>G);
 L4: ADD2 PORT MAP(A=>A4,B=>B4,Cin=>G,S=>S4,CONT=>H);
 L5: ADD2 PORT MAP(A=>A5,B=>B5,Cin=>H,S=>S5,CONT=>I);
 L6: ADD2 PORT MAP(A=>A6,B=>B6,Cin=>I,S=>S6,CONT=>J);
 L7: ADD2 PORT MAP(A=>A7,B=>B7,Cin=>J,S=>S7,CONT=>CONT);
END ARCHITECTURE ADD8;