add2.vhd

来自「组合电路的设计8位加法器设计(ADD8.vhd)」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADD2 IS 
  PORT (A,B,Cin : IN STD_LOGIC;
         CONT,S : OUT STD_LOGIC);  --ABC is input ;s is sum
END ENTITY ADD2;
ARCHITECTURE ADD2 OF ADD2 IS
BEGIN 
 PROCESS(A,B,Cin)
  BEGIN
       IF (A='0'AND B='0'AND Cin='0') THEN S<='0' ; CONT<='0';
    ELSIF (A='0'AND B='0'AND Cin='0') THEN S<='0' ; CONT<='0';
    ELSIF (A='0'AND B='0'AND Cin='1') THEN S<='1' ; CONT<='0';
    ELSIF (A='0'AND B='1'AND Cin='0') THEN S<='1' ; CONT<='0';
    ELSIF (A='0'AND B='1'AND Cin='1') THEN S<='0' ; CONT<='1';
    ELSIF (A='1'AND B='0'AND Cin='0') THEN S<='1' ; CONT<='0';
    ELSIF (A='1'AND B='0'AND Cin='1') THEN S<='0' ; CONT<='1';
    ELSIF (A='1'AND B='1'AND Cin='0') THEN S<='0' ; CONT<='1';
    ELSIF (A='1'AND B='1'AND Cin='1') THEN S<='1' ; CONT<='0';
      ELSE NULL; 
  END IF;
END PROCESS;
END ARCHITECTURE ADD2;