add8.rpt

组合电路的设计8位加法器设计(ADD8.vhd)

Project Information                                d:\vhdl\work1 add8\add8.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/27/2008 10:36:25

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


ADD8


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

add8      EPM7032LC44-6    17       9        0      30      8           93 %

User Pins:                 17       9        0  



Project Information                                d:\vhdl\work1 add8\add8.rpt

** FILE HIERARCHY **



|add2:L0|
|add2:L1|
|add2:L2|
|add2:L3|
|add2:L4|
|add2:L5|
|add2:L6|
|add2:L7|


Device-Specific Information:                       d:\vhdl\work1 add8\add8.rpt
add8

***** Logic for device 'add8' compiled without errors.




Device: EPM7032LC44-6

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF



Device-Specific Information:                       d:\vhdl\work1 add8\add8.rpt
add8

** ERROR SUMMARY **

Info: Chip 'add8' in device 'EPM7032LC44-6' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                               
                                               
                                               
                                               
                    C                          
                    O  V  G  G  G  G  G        
              S  S  N  C  N  N  N  N  N  B  A  
              3  7  T  C  D  D  D  D  D  7  6  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
      S1 |  7                                39 | B4 
      B1 |  8                                38 | S6 
      S0 |  9                                37 | S5 
     GND | 10                                36 | S4 
      S2 | 11                                35 | VCC 
      A0 | 12         EPM7032LC44-6          34 | B3 
      A1 | 13                                33 | B2 
      A2 | 14                                32 | B0 
     VCC | 15                                31 | A7 
      A3 | 16                                30 | GND 
      A4 | 17                                29 | RESERVED 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              B  B  A  C  G  V  R  R  R  R  R  
              5  6  5  0  N  C  E  E  E  E  E  
                          D  C  S  S  S  S  S  
                                E  E  E  E  E  
                                R  R  R  R  R  
                                V  V  V  V  V  
                                E  E  E  E  E  
                                D  D  D  D  D  


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                       d:\vhdl\work1 add8\add8.rpt
add8

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    14/16( 87%)  16/16(100%)   4/16( 25%)  19/36( 52%) 
B:    LC17 - LC32    16/16(100%)  10/16( 62%)   5/16( 31%)  19/36( 52%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            26/32     ( 81%)
Total logic cells used:                         30/32     ( 93%)
Total shareable expanders used:                  8/32     ( 25%)
Total Turbo logic cells used:                   30/32     ( 93%)
Total shareable expanders not available (n/a):   1/32     (  3%)
Average fan-in:                                  3.80
Total fan-in:                                   114

Total input pins required:                      17
Total output pins required:                      9
Total bidirectional pins required:               0
Total logic cells required:                     30
Total flipflops required:                        0
Total product terms required:                   81
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           8

Synthesized logic cells:                        21/  32   ( 65%)



Device-Specific Information:                       d:\vhdl\work1 add8\add8.rpt
add8

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  12    (8)  (A)      INPUT               0      0   0    0    0    1    2  A0
  13    (9)  (A)      INPUT               0      0   0    0    0    1    2  A1
  14   (10)  (A)      INPUT               0      0   0    0    0    1    2  A2
  16   (11)  (A)      INPUT               0      0   0    0    0    1    2  A3
  17   (12)  (A)      INPUT               0      0   0    0    0    1    5  A4
  20   (15)  (A)      INPUT               0      0   0    0    0    1    3  A5
  40   (18)  (B)      INPUT               0      0   0    0    0    1    5  A6
  31   (26)  (B)      INPUT               0      0   0    0    0    0    3  A7
  32   (25)  (B)      INPUT               0      0   0    0    0    1    2  B0
   8    (5)  (A)      INPUT               0      0   0    0    0    1    2  B1
  33   (24)  (B)      INPUT               0      0   0    0    0    1    2  B2
  34   (23)  (B)      INPUT               0      0   0    0    0    1    2  B3
  39   (19)  (B)      INPUT               0      0   0    0    0    1    5  B4
  18   (13)  (A)      INPUT               0      0   0    0    0    1    3  B5
  19   (14)  (A)      INPUT               0      0   0    0    0    1    5  B6
  41   (17)  (B)      INPUT               0      0   0    0    0    0    3  B7
  21   (16)  (A)      INPUT               0      0   0    0    0    1    2  C0


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       d:\vhdl\work1 add8\add8.rpt
add8

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   4      1    A     OUTPUT      t        0      0   0    0    2    0    0  CONT
   9      6    A     OUTPUT      t        1      1   0    3    1    0    0  S0
   7      4    A     OUTPUT      t        1      1   0    2    2    0    0  S1
  11      7    A     OUTPUT      t        1      1   0    2    2    0    0  S2
   6      3    A     OUTPUT      t        1      1   0    2    2    0    0  S3
  36     22    B     OUTPUT      t        1      1   0    2    2    0    0  S4
  37     21    B     OUTPUT      t        1      0   0    2    2    0    0  S5
  38     20    B     OUTPUT      t        1      1   0    2    2    0    0  S6
   5      2    A     OUTPUT      t        0      0   0    0    2    0    0  S7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       d:\vhdl\work1 add8\add8.rpt
add8

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  (8)     5    A       SOFT    s t        0      0   0    3    0    1    0  |ADD2:L0|~243~1
 (14)    10    A      LCELL    s t        1      1   0    3    0    1    2  |ADD2:L0|~279~1
 (21)    16    A       SOFT    s t        0      0   0    2    1    1    0  |ADD2:L1|~243~1
 (13)     9    A      LCELL    s t        1      1   0    2    1    1    2  |ADD2:L1|~279~1
 (16)    11    A       SOFT    s t        0      0   0    2    1    1    0  |ADD2:L2|~243~1
 (18)    13    A      LCELL    s t        1      1   0    2    1    1    2  |ADD2:L2|~279~1
 (19)    14    A       SOFT    s t        0      0   0    2    1    1    0  |ADD2:L3|~243~1
 (12)     8    A      LCELL    s t        1      1   0    2    1    1    5  |ADD2:L3|~279~1
 (27)    29    B       SOFT    s t        0      0   0    2    1    1    0  |ADD2:L4|~243~1
 (33)    24    B       SOFT    s t        0      0   0    2    2    0    2  |ADD2:L4|~275~1
 (32)    25    B      LCELL    s t        1      1   0    2    1    1    4  |ADD2:L4|~279~1
 (31)    26    B       SOFT    s t        0      0   0    2    1    1    0  |ADD2:L5|~243~1
 (24)    32    B      LCELL    s t        1      1   0    4    4    0    1  |ADD2:L5|~279~1~2
 (34)    23    B      LCELL    s t        2      1   1    4    5    1    7  |ADD2:L5|~279~1
 (39)    19    B       SOFT    s t        1      1   0    2    2    1    1  |ADD2:L6|~237~1
 (40)    18    B      LCELL    s t        1      1   0    2    2    0    1  |ADD2:L6|~249~1
 (41)    17    B       SOFT    s t        0      0   0    2    2    0    2  |ADD2:L6|~272~1
 (25)    31    B      LCELL    s t        2      2   0    2    2    0    3  |ADD2:L6|~279~1
 (26)    30    B       SOFT    s t        0      0   0    2    1    1    0  |ADD2:L7|~243~1
 (28)    28    B       SOFT    s t        2      2   0    4    2    2    0  |ADD2:L7|~247~1
 (29)    27    B       SOFT    s t        0      0   0    2    1    1    0  |ADD2:L7|~276~1


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       d:\vhdl\work1 add8\add8.rpt
add8

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                                     Logic cells placed in LAB 'A'
        +--------------------------- LC5 |ADD2:L0|~243~1
        | +------------------------- LC10 |ADD2:L0|~279~1
        | | +----------------------- LC16 |ADD2:L1|~243~1
        | | | +--------------------- LC9 |ADD2:L1|~279~1
        | | | | +------------------- LC11 |ADD2:L2|~243~1
        | | | | | +----------------- LC13 |ADD2:L2|~279~1
        | | | | | | +--------------- LC14 |ADD2:L3|~243~1
        | | | | | | | +------------- LC8 |ADD2:L3|~279~1
        | | | | | | | | +----------- LC1 CONT
        | | | | | | | | | +--------- LC6 S0
        | | | | | | | | | | +------- LC4 S1
        | | | | | | | | | | | +----- LC7 S2
        | | | | | | | | | | | | +--- LC3 S3
        | | | | | | | | | | | | | +- LC2 S7
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'A':
LC5  -> - - - - - - - - - * - - - - | * - | <-- |ADD2:L0|~243~1
LC10 -> - - * * - - - - - - * - - - | * - | <-- |ADD2:L0|~279~1
LC16 -> - - - - - - - - - - * - - - | * - | <-- |ADD2:L1|~243~1
LC9  -> - - - - * * - - - - - * - - | * - | <-- |ADD2:L1|~279~1
LC11 -> - - - - - - - - - - - * - - | * - | <-- |ADD2:L2|~243~1
LC13 -> - - - - - - * * - - - - * - | * - | <-- |ADD2:L2|~279~1
LC14 -> - - - - - - - - - - - - * - | * - | <-- |ADD2:L3|~243~1

Pin
12   -> * * - - - - - - - * - - - - | * - | <-- A0
13   -> - - * * - - - - - - * - - - | * - | <-- A1
14   -> - - - - * * - - - - - * - - | * - | <-- A2
16   -> - - - - - - * * - - - - * - | * - | <-- A3
32   -> * * - - - - - - - * - - - - | * - | <-- B0
8    -> - - * * - - - - - - * - - - | * - | <-- B1
33   -> - - - - * * - - - - - * - - | * - | <-- B2
34   -> - - - - - - * * - - - - * - | * - | <-- B3
21   -> * * - - - - - - - * - - - - | * - | <-- C0
LC30 -> - - - - - - - - - - - - - * | * - | <-- |ADD2:L7|~243~1
LC28 -> - - - - - - - - * - - - - * | * - | <-- |ADD2:L7|~247~1
LC27 -> - - - - - - - - * - - - - - | * - | <-- |ADD2:L7|~276~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       d:\vhdl\work1 add8\add8.rpt
add8

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                         Logic cells placed in LAB 'B'
        +------------------------------- LC29 |ADD2:L4|~243~1
        | +----------------------------- LC24 |ADD2:L4|~275~1
        | | +--------------------------- LC25 |ADD2:L4|~279~1
        | | | +------------------------- LC26 |ADD2:L5|~243~1
        | | | | +----------------------- LC32 |ADD2:L5|~279~1~2
        | | | | | +--------------------- LC23 |ADD2:L5|~279~1
        | | | | | | +------------------- LC19 |ADD2:L6|~237~1
        | | | | | | | +----------------- LC18 |ADD2:L6|~249~1
        | | | | | | | | +--------------- LC17 |ADD2:L6|~272~1
        | | | | | | | | | +------------- LC31 |ADD2:L6|~279~1
        | | | | | | | | | | +----------- LC30 |ADD2:L7|~243~1
        | | | | | | | | | | | +--------- LC28 |ADD2:L7|~247~1
        | | | | | | | | | | | | +------- LC27 |ADD2:L7|~276~1
        | | | | | | | | | | | | | +----- LC22 S4
        | | | | | | | | | | | | | | +--- LC21 S5
        | | | | | | | | | | | | | | | +- LC20 S6
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC29 -> - - - - - - - - - - - - - * - - | - * | <-- |ADD2:L4|~243~1
LC24 -> - - - - * * - - - - - - - - - - | - * | <-- |ADD2:L4|~275~1
LC25 -> - * - * * * - - - - - - - - * - | - * | <-- |ADD2:L4|~279~1
LC26 -> - - - - - - - - - - - - - - * - | - * | <-- |ADD2:L5|~243~1
LC32 -> - - - - - * - - - - - - - - - - | - * | <-- |ADD2:L5|~279~1~2
LC23 -> - - - - * * * * * * - * - - - * | - * | <-- |ADD2:L5|~279~1
LC19 -> - - - - - - - * - - - - - - - * | - * | <-- |ADD2:L6|~237~1
LC18 -> - - - - - - * - - - - - - - - - | - * | <-- |ADD2:L6|~249~1
LC17 -> - - - - - - - - - * - * - - - - | - * | <-- |ADD2:L6|~272~1
LC31 -> - - - - - - - - * - * - * - - - | - * | <-- |ADD2:L6|~279~1

Pin
17   -> * * * - * * - - - - - - - * - - | - * | <-- A4
20   -> - - - * * * - - - - - - - - * - | - * | <-- A5
40   -> - - - - - - * * * * - * - - - * | - * | <-- A6