detect_high.tan.qmsg

利用FPGA实现频率测试,基于VHDL实现,具有良好的测试性能可直接使用

{ "Info" "ITDB_FULL_TCO_RESULT" "clk high_time\[12\] high_time\[12\]~reg0 8.133 ns register " "Info: tco from clock \"clk\" to destination pin \"high_time\[12\]\" through register \"high_time\[12\]~reg0\" is 8.133 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.867 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 55 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 55; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.666 ns) 2.867 ns high_time\[12\]~reg0 3 REG LCFF_X33_Y5_N5 1 " "Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.867 ns; Loc. = LCFF_X33_Y5_N5; Fanout = 1; REG Node = 'high_time\[12\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.588 ns" { clk~clkctrl high_time[12]~reg0 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.99 % ) " "Info: Total cell delay = 1.806 ns ( 62.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.061 ns ( 37.01 % ) " "Info: Total interconnect delay = 1.061 ns ( 37.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.867 ns" { clk clk~clkctrl high_time[12]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.867 ns" { clk clk~combout clk~clkctrl high_time[12]~reg0 } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.962 ns + Longest register pin " "Info: + Longest register to pin delay is 4.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns high_time\[12\]~reg0 1 REG LCFF_X33_Y5_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y5_N5; Fanout = 1; REG Node = 'high_time\[12\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { high_time[12]~reg0 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(3.286 ns) 4.962 ns high_time\[12\] 2 PIN PIN_97 0 " "Info: 2: + IC(1.676 ns) + CELL(3.286 ns) = 4.962 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'high_time\[12\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.962 ns" { high_time[12]~reg0 high_time[12] } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.286 ns ( 66.22 % ) " "Info: Total cell delay = 3.286 ns ( 66.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns ( 33.78 % ) " "Info: Total interconnect delay = 1.676 ns ( 33.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.962 ns" { high_time[12]~reg0 high_time[12] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.962 ns" { high_time[12]~reg0 high_time[12] } { 0.000ns 1.676ns } { 0.000ns 3.286ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.867 ns" { clk clk~clkctrl high_time[12]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.867 ns" { clk clk~combout clk~clkctrl high_time[12]~reg0 } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.962 ns" { high_time[12]~reg0 high_time[12] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.962 ns" { high_time[12]~reg0 high_time[12] } { 0.000ns 1.676ns } { 0.000ns 3.286ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "high_time\[3\]~reg0 reset clk 0.509 ns register " "Info: th for register \"high_time\[3\]~reg0\" (data pin = \"reset\", clock pin = \"clk\") is 0.509 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.862 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 55 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 55; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.917 ns) + CELL(0.666 ns) 2.862 ns high_time\[3\]~reg0 3 REG LCFF_X33_Y6_N27 1 " "Info: 3: + IC(0.917 ns) + CELL(0.666 ns) = 2.862 ns; Loc. = LCFF_X33_Y6_N27; Fanout = 1; REG Node = 'high_time\[3\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.583 ns" { clk~clkctrl high_time[3]~reg0 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.10 % ) " "Info: Total cell delay = 1.806 ns ( 63.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.056 ns ( 36.90 % ) " "Info: Total interconnect delay = 1.056 ns ( 36.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl high_time[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.862 ns" { clk clk~combout clk~clkctrl high_time[3]~reg0 } { 0.000ns 0.000ns 0.139ns 0.917ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.659 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns reset 1 PIN PIN_129 29 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_129; Fanout = 29; PIN Node = 'reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.202 ns) 2.551 ns high_time~1194 2 COMB LCCOMB_X33_Y6_N26 1 " "Info: 2: + IC(1.199 ns) + CELL(0.202 ns) = 2.551 ns; Loc. = LCCOMB_X33_Y6_N26; Fanout = 1; COMB Node = 'high_time~1194'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.401 ns" { reset high_time~1194 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.659 ns high_time\[3\]~reg0 3 REG LCFF_X33_Y6_N27 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.659 ns; Loc. = LCFF_X33_Y6_N27; Fanout = 1; REG Node = 'high_time\[3\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { high_time~1194 high_time[3]~reg0 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.460 ns ( 54.91 % ) " "Info: Total cell delay = 1.460 ns ( 54.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.199 ns ( 45.09 % ) " "Info: Total interconnect delay = 1.199 ns ( 45.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.659 ns" { reset high_time~1194 high_time[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.659 ns" { reset reset~combout high_time~1194 high_time[3]~reg0 } { 0.000ns 0.000ns 1.199ns 0.000ns } { 0.000ns 1.150ns 0.202ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.862 ns" { clk clk~clkctrl high_time[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.862 ns" { clk clk~combout clk~clkctrl high_time[3]~reg0 } { 0.000ns 0.000ns 0.139ns 0.917ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.659 ns" { reset high_time~1194 high_time[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.659 ns" { reset reset~combout high_time~1194 high_time[3]~reg0 } { 0.000ns 0.000ns 1.199ns 0.000ns } { 0.000ns 1.150ns 0.202ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 09 20:47:50 2008 " "Info: Processing ended: Mon Jun 09 20:47:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}