detect_high.vhd

来自「利用FPGA实现频率测试,基于VHDL实现,具有良好的测试性能可直接使用」· VHDL 代码 · 共 51 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY detect_high IS
	PORT(
			clk : IN std_logic;
			reset : IN std_logic;
			enable : IN std_logic;
			high_time : OUT std_logic_vector(26 downto 0)
		);
END detect_high;

ARCHITECTURE plus_cnt OF detect_high IS
SIGNAL count_int:std_logic_vector(26 downto 0); --std_logic_vector(0 to 26);
SIGNAL enable_buf:std_logic;
BEGIN
	PROCESS--(clk,reset)
	BEGIN
		WAIT UNTIL rising_edge(clk);
		IF reset = '1' THEN
			count_int <= (OTHERS => '0');
		ELSE
			IF enable = '0' THEN --100000000-1
				count_int<=(OTHERS => '0');
			ELSE
				count_int <= count_int + 1;
			END IF;
		END IF;
	END PROCESS;
	
	PROCESS --(clk,reset)
	BEGIN
		WAIT UNTIL rising_edge(clk);
			enable_buf <= enable; 
	END PROCESS;
	
	PROCESS--(clk,reset) 
	BEGIN
		WAIT UNTIL rising_edge(clk);
		IF reset = '1' THEN
			high_time <= (OTHERS => '0');
		ELSIF enable = '0' AND enable_buf = '1' THEN
			high_time <= count_int;
		END IF;
	END PROCESS;	
	
	
END plus_cnt;