detect_high.map.summary

来自「利用FPGA实现频率测试,基于VHDL实现,具有良好的测试性能可直接使用」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Mon Jun 09 20:47:23 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : detect_high
Top-level Entity Name : detect_high
Family : Cyclone II
Total logic elements : 56
Total registers : 55
Total pins : 30
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0