📄 detect_high.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count_int\[0\] register count_int\[26\] 226.65 MHz 4.412 ns Internal " "Info: Clock \"clk\" has Internal fmax of 226.65 MHz between source register \"count_int\[0\]\" and destination register \"count_int\[26\]\" (period= 4.412 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.154 ns + Longest register register " "Info: + Longest register to register delay is 4.154 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_int\[0\] 1 REG LCFF_X33_Y5_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y5_N7; Fanout = 3; REG Node = 'count_int\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count_int[0] } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.621 ns) 1.093 ns count_int\[0\]~284 2 COMB LCCOMB_X33_Y5_N6 2 " "Info: 2: + IC(0.472 ns) + CELL(0.621 ns) = 1.093 ns; Loc. = LCCOMB_X33_Y5_N6; Fanout = 2; COMB Node = 'count_int\[0\]~284'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.093 ns" { count_int[0] count_int[0]~284 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.179 ns count_int\[1\]~286 3 COMB LCCOMB_X33_Y5_N8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.179 ns; Loc. = LCCOMB_X33_Y5_N8; Fanout = 2; COMB Node = 'count_int\[1\]~286'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[0]~284 count_int[1]~286 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.265 ns count_int\[2\]~287 4 COMB LCCOMB_X33_Y5_N10 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.265 ns; Loc. = LCCOMB_X33_Y5_N10; Fanout = 2; COMB Node = 'count_int\[2\]~287'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[1]~286 count_int[2]~287 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.351 ns count_int\[3\]~288 5 COMB LCCOMB_X33_Y5_N12 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.351 ns; Loc. = LCCOMB_X33_Y5_N12; Fanout = 2; COMB Node = 'count_int\[3\]~288'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[2]~287 count_int[3]~288 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.541 ns count_int\[4\]~289 6 COMB LCCOMB_X33_Y5_N14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.190 ns) = 1.541 ns; Loc. = LCCOMB_X33_Y5_N14; Fanout = 2; COMB Node = 'count_int\[4\]~289'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { count_int[3]~288 count_int[4]~289 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.627 ns count_int\[5\]~290 7 COMB LCCOMB_X33_Y5_N16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.627 ns; Loc. = LCCOMB_X33_Y5_N16; Fanout = 2; COMB Node = 'count_int\[5\]~290'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[4]~289 count_int[5]~290 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.713 ns count_int\[6\]~291 8 COMB LCCOMB_X33_Y5_N18 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.713 ns; Loc. = LCCOMB_X33_Y5_N18; Fanout = 2; COMB Node = 'count_int\[6\]~291'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[5]~290 count_int[6]~291 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.799 ns count_int\[7\]~292 9 COMB LCCOMB_X33_Y5_N20 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.799 ns; Loc. = LCCOMB_X33_Y5_N20; Fanout = 2; COMB Node = 'count_int\[7\]~292'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[6]~291 count_int[7]~292 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.885 ns count_int\[8\]~293 10 COMB LCCOMB_X33_Y5_N22 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.885 ns; Loc. = LCCOMB_X33_Y5_N22; Fanout = 2; COMB Node = 'count_int\[8\]~293'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[7]~292 count_int[8]~293 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.971 ns count_int\[9\]~294 11 COMB LCCOMB_X33_Y5_N24 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 1.971 ns; Loc. = LCCOMB_X33_Y5_N24; Fanout = 2; COMB Node = 'count_int\[9\]~294'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[8]~293 count_int[9]~294 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.057 ns count_int\[10\]~295 12 COMB LCCOMB_X33_Y5_N26 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.057 ns; Loc. = LCCOMB_X33_Y5_N26; Fanout = 2; COMB Node = 'count_int\[10\]~295'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[9]~294 count_int[10]~295 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.143 ns count_int\[11\]~296 13 COMB LCCOMB_X33_Y5_N28 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.143 ns; Loc. = LCCOMB_X33_Y5_N28; Fanout = 2; COMB Node = 'count_int\[11\]~296'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[10]~295 count_int[11]~296 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 2.318 ns count_int\[12\]~297 14 COMB LCCOMB_X33_Y5_N30 2 " "Info: 14: + IC(0.000 ns) + CELL(0.175 ns) = 2.318 ns; Loc. = LCCOMB_X33_Y5_N30; Fanout = 2; COMB Node = 'count_int\[12\]~297'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.175 ns" { count_int[11]~296 count_int[12]~297 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.404 ns count_int\[13\]~298 15 COMB LCCOMB_X33_Y4_N0 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.404 ns; Loc. = LCCOMB_X33_Y4_N0; Fanout = 2; COMB Node = 'count_int\[13\]~298'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[12]~297 count_int[13]~298 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.490 ns count_int\[14\]~299 16 COMB LCCOMB_X33_Y4_N2 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.490 ns; Loc. = LCCOMB_X33_Y4_N2; Fanout = 2; COMB Node = 'count_int\[14\]~299'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[13]~298 count_int[14]~299 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.576 ns count_int\[15\]~300 17 COMB LCCOMB_X33_Y4_N4 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.576 ns; Loc. = LCCOMB_X33_Y4_N4; Fanout = 2; COMB Node = 'count_int\[15\]~300'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[14]~299 count_int[15]~300 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.662 ns count_int\[16\]~301 18 COMB LCCOMB_X33_Y4_N6 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.662 ns; Loc. = LCCOMB_X33_Y4_N6; Fanout = 2; COMB Node = 'count_int\[16\]~301'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[15]~300 count_int[16]~301 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.748 ns count_int\[17\]~302 19 COMB LCCOMB_X33_Y4_N8 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.748 ns; Loc. = LCCOMB_X33_Y4_N8; Fanout = 2; COMB Node = 'count_int\[17\]~302'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[16]~301 count_int[17]~302 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.834 ns count_int\[18\]~303 20 COMB LCCOMB_X33_Y4_N10 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 2.834 ns; Loc. = LCCOMB_X33_Y4_N10; Fanout = 2; COMB Node = 'count_int\[18\]~303'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[17]~302 count_int[18]~303 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.920 ns count_int\[19\]~304 21 COMB LCCOMB_X33_Y4_N12 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 2.920 ns; Loc. = LCCOMB_X33_Y4_N12; Fanout = 2; COMB Node = 'count_int\[19\]~304'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[18]~303 count_int[19]~304 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 3.110 ns count_int\[20\]~305 22 COMB LCCOMB_X33_Y4_N14 2 " "Info: 22: + IC(0.000 ns) + CELL(0.190 ns) = 3.110 ns; Loc. = LCCOMB_X33_Y4_N14; Fanout = 2; COMB Node = 'count_int\[20\]~305'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { count_int[19]~304 count_int[20]~305 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.196 ns count_int\[21\]~306 23 COMB LCCOMB_X33_Y4_N16 2 " "Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.196 ns; Loc. = LCCOMB_X33_Y4_N16; Fanout = 2; COMB Node = 'count_int\[21\]~306'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[20]~305 count_int[21]~306 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.282 ns count_int\[22\]~307 24 COMB LCCOMB_X33_Y4_N18 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.282 ns; Loc. = LCCOMB_X33_Y4_N18; Fanout = 2; COMB Node = 'count_int\[22\]~307'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[21]~306 count_int[22]~307 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.368 ns count_int\[23\]~308 25 COMB LCCOMB_X33_Y4_N20 2 " "Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.368 ns; Loc. = LCCOMB_X33_Y4_N20; Fanout = 2; COMB Node = 'count_int\[23\]~308'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[22]~307 count_int[23]~308 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.454 ns count_int\[24\]~309 26 COMB LCCOMB_X33_Y4_N22 2 " "Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.454 ns; Loc. = LCCOMB_X33_Y4_N22; Fanout = 2; COMB Node = 'count_int\[24\]~309'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[23]~308 count_int[24]~309 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.540 ns count_int\[25\]~310 27 COMB LCCOMB_X33_Y4_N24 1 " "Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.540 ns; Loc. = LCCOMB_X33_Y4_N24; Fanout = 1; COMB Node = 'count_int\[25\]~310'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { count_int[24]~309 count_int[25]~310 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.046 ns count_int\[26\]~276 28 COMB LCCOMB_X33_Y4_N26 1 " "Info: 28: + IC(0.000 ns) + CELL(0.506 ns) = 4.046 ns; Loc. = LCCOMB_X33_Y4_N26; Fanout = 1; COMB Node = 'count_int\[26\]~276'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { count_int[25]~310 count_int[26]~276 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.154 ns count_int\[26\] 29 REG LCFF_X33_Y4_N27 2 " "Info: 29: + IC(0.000 ns) + CELL(0.108 ns) = 4.154 ns; Loc. = LCFF_X33_Y4_N27; Fanout = 2; REG Node = 'count_int\[26\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { count_int[26]~276 count_int[26] } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.682 ns ( 88.64 % ) " "Info: Total cell delay = 3.682 ns ( 88.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.472 ns ( 11.36 % ) " "Info: Total interconnect delay = 0.472 ns ( 11.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.154 ns" { count_int[0] count_int[0]~284 count_int[1]~286 count_int[2]~287 count_int[3]~288 count_int[4]~289 count_int[5]~290 count_int[6]~291 count_int[7]~292 count_int[8]~293 count_int[9]~294 count_int[10]~295 count_int[11]~296 count_int[12]~297 count_int[13]~298 count_int[14]~299 count_int[15]~300 count_int[16]~301 count_int[17]~302 count_int[18]~303 count_int[19]~304 count_int[20]~305 count_int[21]~306 count_int[22]~307 count_int[23]~308 count_int[24]~309 count_int[25]~310 count_int[26]~276 count_int[26] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.154 ns" { count_int[0] count_int[0]~284 count_int[1]~286 count_int[2]~287 count_int[3]~288 count_int[4]~289 count_int[5]~290 count_int[6]~291 count_int[7]~292 count_int[8]~293 count_int[9]~294 count_int[10]~295 count_int[11]~296 count_int[12]~297 count_int[13]~298 count_int[14]~299 count_int[15]~300 count_int[16]~301 count_int[17]~302 count_int[18]~303 count_int[19]~304 count_int[20]~305 count_int[21]~306 count_int[22]~307 count_int[23]~308 count_int[24]~309 count_int[25]~310 count_int[26]~276 count_int[26] } { 0.000ns 0.472ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.006 ns - Smallest " "Info: - Smallest clock skew is 0.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.873 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 55 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 55; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.928 ns) + CELL(0.666 ns) 2.873 ns count_int\[26\] 3 REG LCFF_X33_Y4_N27 2 " "Info: 3: + IC(0.928 ns) + CELL(0.666 ns) = 2.873 ns; Loc. = LCFF_X33_Y4_N27; Fanout = 2; REG Node = 'count_int\[26\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.594 ns" { clk~clkctrl count_int[26] } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.86 % ) " "Info: Total cell delay = 1.806 ns ( 62.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.067 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.067 ns ( 37.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.873 ns" { clk clk~clkctrl count_int[26] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.873 ns" { clk clk~combout clk~clkctrl count_int[26] } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.867 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 55 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 55; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.666 ns) 2.867 ns count_int\[0\] 3 REG LCFF_X33_Y5_N7 3 " "Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.867 ns; Loc. = LCFF_X33_Y5_N7; Fanout = 3; REG Node = 'count_int\[0\]'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.588 ns" { clk~clkctrl count_int[0] } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.99 % ) " "Info: Total cell delay = 1.806 ns ( 62.99 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.061 ns ( 37.01 % ) " "Info: Total interconnect delay = 1.061 ns ( 37.01 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.867 ns" { clk clk~clkctrl count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.867 ns" { clk clk~combout clk~clkctrl count_int[0] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.873 ns" { clk clk~clkctrl count_int[26] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.873 ns" { clk clk~combout clk~clkctrl count_int[26] } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.867 ns" { clk clk~clkctrl count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.867 ns" { clk clk~combout clk~clkctrl count_int[0] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 30 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.154 ns" { count_int[0] count_int[0]~284 count_int[1]~286 count_int[2]~287 count_int[3]~288 count_int[4]~289 count_int[5]~290 count_int[6]~291 count_int[7]~292 count_int[8]~293 count_int[9]~294 count_int[10]~295 count_int[11]~296 count_int[12]~297 count_int[13]~298 count_int[14]~299 count_int[15]~300 count_int[16]~301 count_int[17]~302 count_int[18]~303 count_int[19]~304 count_int[20]~305 count_int[21]~306 count_int[22]~307 count_int[23]~308 count_int[24]~309 count_int[25]~310 count_int[26]~276 count_int[26] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.154 ns" { count_int[0] count_int[0]~284 count_int[1]~286 count_int[2]~287 count_int[3]~288 count_int[4]~289 count_int[5]~290 count_int[6]~291 count_int[7]~292 count_int[8]~293 count_int[9]~294 count_int[10]~295 count_int[11]~296 count_int[12]~297 count_int[13]~298 count_int[14]~299 count_int[15]~300 count_int[16]~301 count_int[17]~302 count_int[18]~303 count_int[19]~304 count_int[20]~305 count_int[21]~306 count_int[22]~307 count_int[23]~308 count_int[24]~309 count_int[25]~310 count_int[26]~276 count_int[26] } { 0.000ns 0.472ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.873 ns" { clk clk~clkctrl count_int[26] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.873 ns" { clk clk~combout clk~clkctrl count_int[26] } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.867 ns" { clk clk~clkctrl count_int[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.867 ns" { clk clk~combout clk~clkctrl count_int[0] } { 0.000ns 0.000ns 0.139ns 0.922ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "high_time\[24\]~reg0 enable clk 1.849 ns register " "Info: tsu for register \"high_time\[24\]~reg0\" (data pin = \"enable\", clock pin = \"clk\") is 1.849 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.762 ns + Longest pin register " "Info: + Longest pin to register delay is 4.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns enable 1 PIN PIN_130 3 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_130; Fanout = 3; PIN Node = 'enable'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { enable } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.615 ns) 2.841 ns high_time\[0\]~1191 2 COMB LCCOMB_X33_Y6_N20 27 " "Info: 2: + IC(1.076 ns) + CELL(0.615 ns) = 2.841 ns; Loc. = LCCOMB_X33_Y6_N20; Fanout = 27; COMB Node = 'high_time\[0\]~1191'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.691 ns" { enable high_time[0]~1191 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.855 ns) 4.762 ns high_time\[24\]~reg0 3 REG LCFF_X33_Y4_N31 1 " "Info: 3: + IC(1.066 ns) + CELL(0.855 ns) = 4.762 ns; Loc. = LCFF_X33_Y4_N31; Fanout = 1; REG Node = 'high_time\[24\]~reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.921 ns" { high_time[0]~1191 high_time[24]~reg0 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.620 ns ( 55.02 % ) " "Info: Total cell delay = 2.620 ns ( 55.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.142 ns ( 44.98 % ) " "Info: Total interconnect delay = 2.142 ns ( 44.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.762 ns" { enable high_time[0]~1191 high_time[24]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.762 ns" { enable enable~combout high_time[0]~1191 high_time[24]~reg0 } { 0.000ns 0.000ns 1.076ns 1.066ns } { 0.000ns 1.150ns 0.615ns 0.855ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.873 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 55 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 55; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.928 ns) + CELL(0.666 ns) 2.873 ns high_time\[24\]~reg0 3 REG LCFF_X33_Y4_N31 1 " "Info: 3: + IC(0.928 ns) + CELL(0.666 ns) = 2.873 ns; Loc. = LCFF_X33_Y4_N31; Fanout = 1; REG Node = 'high_time\[24\]~reg0'" { } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.594 ns" { clk~clkctrl high_time[24]~reg0 } "NODE_NAME" } } { "detect_high.vhd" "" { Text "E:/tool_stud/cnt_high/detect_high.vhd" 46 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.86 % ) " "Info: Total cell delay = 1.806 ns ( 62.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.067 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.067 ns ( 37.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.873 ns" { clk clk~clkctrl high_time[24]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.873 ns" { clk clk~combout clk~clkctrl high_time[24]~reg0 } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.762 ns" { enable high_time[0]~1191 high_time[24]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.762 ns" { enable enable~combout high_time[0]~1191 high_time[24]~reg0 } { 0.000ns 0.000ns 1.076ns 1.066ns } { 0.000ns 1.150ns 0.615ns 0.855ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.873 ns" { clk clk~clkctrl high_time[24]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.873 ns" { clk clk~combout clk~clkctrl high_time[24]~reg0 } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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