detect_high.fit.summary

利用FPGA实现频率测试,基于VHDL实现,具有良好的测试性能可直接使用

Fitter Status : Successful - Mon Jun 09 20:47:41 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : detect_high
Top-level Entity Name : detect_high
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
Total logic elements : 56 / 8,256 ( < 1 % )
Total registers : 55
Total pins : 30 / 138 ( 22 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )