an_dcfifo_top.qarlog

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输

******* Archived project restoration attempt on Wed Aug 27 15:58:13 2008
Source archive file:	D:/design/an_dcfifo_top.qar
Archive was extracted into	D:/design/an_dcfifo_top_restored
		 - successfully.