an_dcfifo_top_fast_to_slow.sdc

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输

## Generated SDC file "an_dcfifo_top.sdc"

## Copyright (C) 1991-2007 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.


## VENDOR  "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

## DATE    "Fri Oct 05 10:07:40 2007"

##
## DEVICE  "EP3SE50F484C2"
##


#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3



#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {rvclk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {rvclk}] -add
create_clock -name {trclk} -period 2.500 -waveform { 0.000 1.250 } [get_ports {trclk}] -add


#**************************************************************
# Create Generated Clock
#**************************************************************



#**************************************************************
# Set Clock Latency
#**************************************************************



#**************************************************************
# Set Clock Uncertainty
#**************************************************************



#**************************************************************
# Set Input Delay
#**************************************************************



#**************************************************************
# Set Output Delay
#**************************************************************



#**************************************************************
# Set Clock Groups
#**************************************************************



#**************************************************************
# Set False Path
#**************************************************************

# If rvclk and trclk are asyncrhnous use the following command
set_false_path  -from  [get_clocks {rvclk}]  -to  [get_clocks {trclk}]
set_false_path  -from  [get_clocks {trclk}]  -to  [get_clocks {rvclk}]

# If rvclk and trclk are synnchronous use the following command.
#set_false_path  -from  [get_registers {*dcfifo*delayed_wrptr_g[*]}]  -to  [get_registers {*dcfifo*rs_dgwp*}]
#set_false_path  -from  [get_registers {*dcfifo*rdptr_g[*]}]  -to  [get_registers {*dcfifo*ws_dgrp*}]



#**************************************************************
# Set Multicycle Path
#**************************************************************



#**************************************************************
# Set Maximum Delay
#**************************************************************



#**************************************************************
# Set Minimum Delay
#**************************************************************



#**************************************************************
# Set Input Transition
#**************************************************************



#**************************************************************
# Set Load
#**************************************************************