an_dcfifo_top.qws

来自「alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 」· QWS 代码 · 共 39 行

[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=an_dcfifo_top.v
DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
[ProjectWorkspace.Frames.ChildFrames.Document-1]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
DocPathName=read_control_logic.v
DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
[ProjectWorkspace.Frames.ChildFrames.Document-2]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0]
DocPathName=write_control_logic.v
DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=True
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap]
AFC_IN_REPORT=False