fast_to_slow_rtl.do

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输

transcript on
if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -vlog01compat -work work ../../dcfifo8X32.v
vlog -vlog01compat -work work ../../rom256X32.v
vlog -vlog01compat -work work ../../ram256X32.v
vlog -vlog01compat -work work ../../write_control_logic.v
vlog -vlog01compat -work work ../../read_control_logic.v
vlog -vlog01compat -work work ../../an_dcfifo_top.v

vlog -vlog01compat -work work an_dcfifo_top_fast_to_slow.vt

vsim -t 1ps -L lpm_ver -L altera_ver -L altera_mf_ver -L sgate_ver -L rtl_work -L work an_dcfifo_top_vlg_vec_tst

do rtl_wave.do
view structure
view signals
run -all