an_dcfifo_top_fast_to_slow.vt

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "11/06/2007 13:51:20"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          an_dcfifo_top
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module an_dcfifo_top_vlg_vec_tst();
// constants                                           
// general purpose registers
reg reset;
reg rvclk;
reg trclk;
// wires                                               
wire [31:0] q;
wire [8:0] word_count;

// assign statements (if any)                          
an_dcfifo_top i1 (
// port map - connection between master ports and signals/registers   
	.q(q),
	.reset(reset),
	.rvclk(rvclk),
	.trclk(trclk),
	.word_count(word_count)
);
initial 
begin 
#5200000 $stop;
end 

// reset
initial
begin
	reset = 1'b1;
	reset = #10000 1'b0;
end 

// trclk
always
begin
	trclk = 1'b0;
	trclk = #1250 1'b1;
	#1250;
end 

// rvclk
always
begin
	rvclk = 1'b0;
	rvclk = #5000 1'b1;
	#5000;
end 
endmodule