📄 an_dcfifo_top_v.sdo

📁 alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输
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    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (312:312:312) (304:304:304))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe11a\[2\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (634:634:634) (610:610:610))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe11a\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe12a\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT asdata (573:573:573) (614:614:614))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT asdata (566:566:566) (603:603:603))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe11a\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT asdata (894:894:894) (950:950:950))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe12a\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT asdata (502:502:502) (543:543:543))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdempty_eq_comp_aeb_int\~54)
    (DELAY
      (ABSOLUTE
        (PORT dataa (254:254:254) (245:245:245))
        (PORT datad (244:244:244) (231:231:231))
        (PORT dataf (253:253:253) (241:241:241))
        (IOPATH dataa combout (400:400:400) (367:367:367))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdempty_eq_comp_aeb_int\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (274:274:274) (263:263:263))
        (PORT datac (276:276:276) (266:266:266))
        (PORT datad (250:250:250) (240:240:240))
        (PORT dataf (228:228:228) (236:236:236))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datac combout (246:246:246) (243:243:243))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE rdctrl_logic\|Selector0\~44)
    (DELAY
      (ABSOLUTE
        (PORT datab (244:244:244) (254:254:254))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datae combout (352:352:352) (345:345:345))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rdctrl_logic\|state\.INCADR)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE rdctrl_logic\|state\~138DUPLICATE)
    (DELAY
      (ABSOLUTE
        (PORT dataa (258:258:258) (247:247:247))
        (PORT datab (265:265:265) (254:254:254))
        (PORT datac (260:260:260) (248:248:248))
        (PORT datad (266:266:266) (256:256:256))
        (PORT dataf (244:244:244) (249:249:249))
        (IOPATH dataa combout (400:400:400) (367:367:367))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datac combout (246:246:246) (243:243:243))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rdctrl_logic\|state\.IDLE\~DUPLICATE)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE rdctrl_logic\|Selector1\~61)
    (DELAY
      (ABSOLUTE
        (PORT datab (253:253:253) (244:244:244))
        (PORT datad (300:300:300) (290:290:290))
        (PORT dataf (256:256:256) (260:260:260))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rdctrl_logic\|state\.WAIT)
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE rdctrl_logic\|word_count_o\[0\]\~77)
    (DELAY
      (ABSOLUTE
        (PORT dataa (266:266:266) (255:255:255))
        (PORT datab (260:260:260) (250:250:250))
        (PORT datad (256:256:256) (245:245:245))
        (PORT dataf (243:243:243) (249:249:249))
        (IOPATH dataa combout (400:400:400) (367:367:367))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rdctrl_logic\|word_count_o\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1585:1585:1585) (1552:1552:1552))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1415:1415:1415) (1404:1404:1404))
        (PORT sclr (2338:2338:2338) (2211:2211:2211))
        (PORT ena (2139:2139:2139) (2095:2095:2095))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE rdctrl_logic\|Add1\~140)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rdctrl_logic\|word_count_o\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1585:1585:1585) (1552:1552:1552))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1415:1415:1415) (1404:1404:1404))
        (PORT sclr (2338:2338:2338) (2211:2211:2211))
        (PORT ena (2139:2139:2139) (2095:2095:2095))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE rdctrl_logic\|Add1\~144)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rdctrl_logic\|word_count_o\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1585:1585:1585) (1552:1552:1552))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1415:1415:1415) (1404:1404:1404))
        (PORT sclr (2338:2338:2338) (2211:2211:2211))
        (PORT ena (2139:2139:2139) (2095:2095:2095))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE rdctrl_logic\|Add1\~148)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rdctrl_logic\|word_count_o\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1585:1585:1585) (1552:1552:1552))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1415:1415:1415) (1404:1404:1404))
        (PORT sclr (2338:2338:2338) (2211:2211:2211))
        (PORT ena (2139:2139:2139) (2095:2095:2095))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE rdctrl_logic\|Add1\~152)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE rdctrl_logic\|word_count_o\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1585:1585:1585) (1552:1552:1552))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1415:1415:1415) (1404:1404:1404))
        (PORT sclr (2338:2338:2338) (2211:2211:2211))
        (PORT ena (2139:2139:2139) (2095:2095:2095))
        (IOPATH (posedge clk
上一页 1 2 3 45
💿 文件大小 908 K
👤 上传用户 pore
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#alteral #VERILOG #DCFIFO #FPGA
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