📄 an_dcfifo_top_v.sdo

📁 alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输
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        (PORT ena (700:700:700) (603:603:603))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Add0\~132)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|addr_o\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (PORT sclr (840:840:840) (764:764:764))
        (PORT ena (700:700:700) (603:603:603))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Add0\~136)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|addr_o\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (PORT sclr (840:840:840) (764:764:764))
        (PORT ena (700:700:700) (603:603:603))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Add0\~140)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|addr_o\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (PORT sclr (840:840:840) (764:764:764))
        (PORT ena (700:700:700) (603:603:603))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Add0\~144)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|addr_o\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (PORT sclr (840:840:840) (764:764:764))
        (PORT ena (700:700:700) (603:603:603))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Add0\~148)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH cin sumout (340:340:340) (287:287:287))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|addr_o\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (PORT sclr (840:840:840) (764:764:764))
        (PORT ena (700:700:700) (603:603:603))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Equal0\~34)
    (DELAY
      (ABSOLUTE
        (PORT dataa (265:265:265) (254:254:254))
        (PORT datab (259:259:259) (250:250:250))
        (PORT datac (267:267:267) (256:256:256))
        (PORT datad (248:248:248) (235:235:235))
        (PORT dataf (251:251:251) (239:239:239))
        (IOPATH dataa combout (404:404:404) (372:372:372))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datac combout (232:232:232) (237:237:237))
        (IOPATH datad combout (236:236:236) (215:215:215))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Equal0\~35)
    (DELAY
      (ABSOLUTE
        (PORT datab (258:258:258) (248:248:248))
        (PORT datac (259:259:259) (247:247:247))
        (PORT datad (245:245:245) (232:232:232))
        (PORT dataf (125:125:125) (135:135:135))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datac combout (232:232:232) (237:237:237))
        (IOPATH datad combout (236:236:236) (215:215:215))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|state\.DONE\~25)
    (DELAY
      (ABSOLUTE
        (PORT datac (323:323:323) (317:317:317))
        (PORT dataf (184:184:184) (195:195:195))
        (IOPATH datac combout (246:246:246) (243:243:243))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|state\.DONE)
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Selector0\~52)
    (DELAY
      (ABSOLUTE
        (PORT dataa (346:346:346) (336:336:336))
        (PORT datac (128:128:128) (139:139:139))
        (PORT datad (478:478:478) (471:471:471))
        (PORT dataf (317:317:317) (307:307:307))
        (IOPATH dataa combout (400:400:400) (367:367:367))
        (IOPATH datac combout (246:246:246) (243:243:243))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|state\.WRITE)
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|counter8a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (PORT ena (816:816:816) (740:740:740))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT asdata (576:576:576) (614:614:614))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe11a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT asdata (895:895:895) (948:948:948))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe12a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT asdata (495:495:495) (532:532:532))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (323:323:323) (310:310:310))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe11a\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (541:541:541) (524:524:524))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe11a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe10\|dffe12a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1611:1611:1611) (1584:1584:1584))
        (PORT asdata (497:497:497) (537:537:537))
        (PORT clrn (1438:1438:1438) (1434:1434:1434))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
💿 文件大小 908 K
👤 上传用户 pore
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#alteral #VERILOG #DCFIFO #FPGA
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