📄 an_dcfifo_top_v.sdo

📁 alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输
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    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|counter8a\[2\]\~33)
    (DELAY
      (ABSOLUTE
        (PORT dataa (274:274:274) (264:264:264))
        (PORT datab (264:264:264) (255:255:255))
        (PORT datac (379:379:379) (367:367:367))
        (PORT dataf (338:338:338) (326:326:326))
        (IOPATH dataa combout (404:404:404) (372:372:372))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datac combout (232:232:232) (237:237:237))
        (IOPATH datad combout (425:425:425) (403:403:403))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrptr_gp\|counter8a\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter3a3\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (274:274:274) (261:261:261))
        (PORT datab (270:270:270) (260:260:260))
        (PORT datac (515:515:515) (494:494:494))
        (PORT datad (274:274:274) (263:263:263))
        (IOPATH dataa combout (400:400:400) (367:367:367))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datac combout (246:246:246) (243:243:243))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH datae combout (352:352:352) (345:345:345))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter3a3)
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT asdata (501:501:501) (540:540:540))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (PORT ena (1080:1080:1080) (1014:1014:1014))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe13\|dffe14a\[3\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (661:661:661) (641:641:641))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe13\|dffe14a\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe13\|dffe15a\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT asdata (573:573:573) (611:611:611))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter3a2\~7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (286:286:286) (273:273:273))
        (PORT datac (268:268:268) (256:256:256))
        (PORT datad (554:554:554) (532:532:532))
        (PORT dataf (258:258:258) (246:246:246))
        (IOPATH dataa combout (400:400:400) (367:367:367))
        (IOPATH datac combout (246:246:246) (243:243:243))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter3a2)
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|rdptr_g\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1615:1615:1615) (1586:1586:1586))
        (PORT asdata (503:503:503) (541:541:541))
        (PORT clrn (1442:1442:1442) (1436:1436:1436))
        (PORT ena (1080:1080:1080) (1014:1014:1014))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe13\|dffe14a\[2\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT dataf (729:729:729) (711:711:711))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe13\|dffe14a\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe13\|dffe15a\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT asdata (575:575:575) (613:613:613))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|wrfull_eq_comp_aeb_int\~64)
    (DELAY
      (ABSOLUTE
        (PORT dataa (248:248:248) (239:239:239))
        (PORT datab (263:263:263) (254:254:254))
        (PORT datac (256:256:256) (245:245:245))
        (PORT datad (265:265:265) (254:254:254))
        (PORT dataf (238:238:238) (225:225:225))
        (IOPATH dataa combout (400:400:400) (367:367:367))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datac combout (246:246:246) (243:243:243))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Add0\~120)
    (DELAY
      (ABSOLUTE
        (PORT dataf (187:187:187) (199:199:199))
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH dataf sumout (578:578:578) (527:527:527))
        (IOPATH dataf cout (359:359:359) (359:359:359))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe13\|dffe14a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT asdata (863:863:863) (918:918:918))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE mydcfifo\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe13\|dffe15a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT asdata (575:575:575) (614:614:614))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP asdata (posedge clk) (79:79:79))
      (HOLD asdata (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|state\.IDLE\~70)
    (DELAY
      (ABSOLUTE
        (PORT datab (325:325:325) (317:317:317))
        (PORT datad (329:329:329) (320:320:320))
        (PORT dataf (190:190:190) (202:202:202))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datad combout (250:250:250) (248:248:248))
        (IOPATH datae combout (352:352:352) (345:345:345))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|state\.IDLE)
    (DELAY
      (ABSOLUTE
        (PORT clk (1614:1614:1614) (1586:1586:1586))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1441:1441:1441) (1436:1436:1436))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|addr_o\[0\]\~154)
    (DELAY
      (ABSOLUTE
        (PORT dataa (274:274:274) (264:264:264))
        (PORT datab (264:264:264) (255:255:255))
        (PORT datac (327:327:327) (317:317:317))
        (PORT dataf (232:232:232) (240:240:240))
        (IOPATH dataa combout (404:404:404) (372:372:372))
        (IOPATH datab combout (411:411:411) (366:366:366))
        (IOPATH datac combout (232:232:232) (237:237:237))
        (IOPATH datad combout (425:425:425) (403:403:403))
        (IOPATH dataf combout (77:77:77) (73:73:73))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|addr_o\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (PORT sclr (840:840:840) (764:764:764))
        (PORT ena (700:700:700) (603:603:603))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Add0\~124)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|addr_o\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (PORT sclr (840:840:840) (764:764:764))
        (PORT ena (700:700:700) (603:603:603))
        (IOPATH (posedge clk) q (65:65:65) (65:65:65))
        (IOPATH (negedge clrn) q (197:197:197) (197:197:197))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (79:79:79))
      (SETUP sclr (posedge clk) (79:79:79))
      (SETUP ena (posedge clk) (79:79:79))
      (HOLD d (posedge clk) (39:39:39))
      (HOLD sclr (posedge clk) (39:39:39))
      (HOLD ena (posedge clk) (39:39:39))
    )
  )
  (CELL
    (CELLTYPE "stratixiii_lcell_comb")
    (INSTANCE wrctrl_logic\|Add0\~128)
    (DELAY
      (ABSOLUTE
        (IOPATH datad sumout (758:758:758) (731:731:731))
        (IOPATH datad cout (515:515:515) (515:515:515))
        (IOPATH cin sumout (340:340:340) (287:287:287))
        (IOPATH cin cout (19:19:19) (19:19:19))
      )
    )
  )
  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE wrctrl_logic\|addr_o\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1613:1613:1613) (1585:1585:1585))
        (PORT d (82:82:82) (76:76:76))
        (PORT clrn (1440:1440:1440) (1435:1435:1435))
        (PORT sclr (840:840:840) (764:764:764))
💿 文件大小 908 K
👤 上传用户 pore
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#alteral #VERILOG #DCFIFO #FPGA
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