📄 asyn_fifo_v.sdo

📁 FPGA VERILOG 用DCFIFO实现跨时钟域的数据传输
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  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|counter_ffa\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.713:1.713:1.713) (1.713:1.713:1.713))
        (PORT sdata (1.314:1.314:1.314) (1.314:1.314:1.314))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[7\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (0.348:0.348:0.348) (0.348:0.348:0.348))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.711:1.711:1.711) (1.711:1.711:1.711))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.711:1.711:1.711) (1.711:1.711:1.711))
        (PORT sdata (0.78:0.78:0.78) (0.78:0.78:0.78))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[7\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT sdata (1.342:1.342:1.342) (1.342:1.342:1.342))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (PORT ena (1.611:1.611:1.611) (1.611:1.611:1.611))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
      (HOLD ena (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdempty_eq_comp_aeb_int\~86)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.383:0.383:0.383) (0.383:0.383:0.383))
        (PORT datab (0.596:0.596:0.596) (0.596:0.596:0.596))
        (PORT datad (0.605:0.605:0.605) (0.605:0.605:0.605))
        (IOPATH dataa combout (0.541:0.541:0.541) (0.541:0.541:0.541))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datac combout (0.358:0.358:0.358) (0.358:0.358:0.358))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|countera4)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.411:0.411:0.411) (0.411:0.411:0.411))
        (PORT datab (0.384:0.384:0.384) (0.384:0.384:0.384))
        (IOPATH dataa combout (0.545:0.545:0.545) (0.545:0.545:0.545))
        (IOPATH dataa cout (0.62:0.62:0.62) (0.62:0.62:0.62))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
        (IOPATH cin combout (0.458:0.458:0.458) (0.458:0.458:0.458))
        (IOPATH cin cout (0.174:0.174:0.174) (0.174:0.174:0.174))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|countera5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.401:0.401:0.401) (0.401:0.401:0.401))
        (PORT datab (0.386:0.386:0.386) (0.386:0.386:0.386))
        (IOPATH dataa combout (0.542:0.542:0.542) (0.542:0.542:0.542))
        (IOPATH datab combout (0.491:0.491:0.491) (0.491:0.491:0.491))
        (IOPATH datab cout (0.495:0.495:0.495) (0.495:0.495:0.495))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
        (IOPATH cin combout (0.458:0.458:0.458) (0.458:0.458:0.458))
        (IOPATH cin cout (0.08:0.08:0.08) (0.08:0.08:0.08))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|counter_ffa\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT sdata (1.039:1.039:1.039) (1.039:1.039:1.039))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[5\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (0.352:0.352:0.352) (0.352:0.352:0.352))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT sdata (0.776:0.776:0.776) (0.776:0.776:0.776))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|countera8)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.412:0.412:0.412) (0.412:0.412:0.412))
        (PORT datab (0.39:0.39:0.39) (0.39:0.39:0.39))
        (IOPATH dataa combout (0.545:0.545:0.545) (0.545:0.545:0.545))
        (IOPATH dataa cout (0.517:0.517:0.517) (0.517:0.517:0.517))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
        (IOPATH cin combout (0.458:0.458:0.458) (0.458:0.458:0.458))
        (IOPATH cin cout (0.08:0.08:0.08) (0.08:0.08:0.08))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|countera9)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.411:0.411:0.411) (0.411:0.411:0.411))
        (PORT datab (0.39:0.39:0.39) (0.39:0.39:0.39))
        (IOPATH dataa combout (0.542:0.542:0.542) (0.542:0.542:0.542))
        (IOPATH datab combout (0.491:0.491:0.491) (0.491:0.491:0.491))
        (IOPATH datab cout (0.495:0.495:0.495) (0.495:0.495:0.495))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
        (IOPATH cin combout (0.458:0.458:0.458) (0.458:0.458:0.458))
        (IOPATH cin cout (0.08:0.08:0.08) (0.08:0.08:0.08))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|counter_ffa\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (0.886:0.886:0.886) (0.886:0.886:0.886))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[9\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (0.354:0.354:0.354) (0.354:0.354:0.354))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT sdata (0.779:0.779:0.779) (0.779:0.779:0.779))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[9\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (1.318:1.318:1.318) (1.318:1.318:1.318))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:
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