asyn_fifo_v.sdo

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输

        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[8\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (0.58:0.58:0.58) (0.58:0.58:0.58))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.706:1.706:1.706) (1.706:1.706:1.706))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.709:1.709:1.709) (1.709:1.709:1.709))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.716:1.716:1.716) (1.716:1.716:1.716))
        (PORT sdata (1.348:1.348:1.348) (1.348:1.348:1.348))
        (PORT aclr (1.719:1.719:1.719) (1.719:1.719:1.719))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter_ffa\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.716:1.716:1.716) (1.716:1.716:1.716))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.71:1.71:1.71) (1.71:1.71:1.71))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[8\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (1.233:1.233:1.233) (1.233:1.233:1.233))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (PORT ena (1.611:1.611:1.611) (1.611:1.611:1.611))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
      (HOLD ena (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdempty_eq_comp_aeb_int\~90)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.601:0.601:0.601) (0.601:0.601:0.601))
        (PORT datab (0.897:0.897:0.897) (0.897:0.897:0.897))
        (PORT datad (0.875:0.875:0.875) (0.875:0.875:0.875))
        (IOPATH dataa combout (0.541:0.541:0.541) (0.541:0.541:0.541))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datac combout (0.358:0.358:0.358) (0.358:0.358:0.358))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|valid_rdreq)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.388:0.388:0.388) (0.388:0.388:0.388))
        (PORT datab (0.311:0.311:0.311) (0.311:0.311:0.311))
        (PORT datac (0.547:0.547:0.547) (0.547:0.547:0.547))
        (PORT datad (0.482:0.482:0.482) (0.482:0.482:0.482))
        (IOPATH dataa combout (0.545:0.545:0.545) (0.545:0.545:0.545))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datac combout (0.322:0.322:0.322) (0.322:0.322:0.322))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT sdata (1.387:1.387:1.387) (1.387:1.387:1.387))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (PORT ena (1.611:1.611:1.611) (1.611:1.611:1.611))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
      (HOLD ena (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (0.897:0.897:0.897) (0.897:0.897:0.897))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.713:1.713:1.713) (1.713:1.713:1.713))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[6\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (0.358:0.358:0.358) (0.358:0.358:0.358))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.711:1.711:1.711) (1.711:1.711:1.711))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.711:1.711:1.711) (1.711:1.711:1.711))
        (PORT sdata (0.78:0.78:0.78) (0.78:0.78:0.78))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter_ffa\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.716:1.716:1.716) (1.716:1.716:1.716))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.71:1.71:1.71) (1.71:1.71:1.71))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[6\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (0.941:0.941:0.941) (0.941:0.941:0.941))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (PORT ena (1.611:1.611:1.611) (1.611:1.611:1.611))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
      (HOLD ena (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdempty_eq_comp_aeb_int\~84)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.375:0.375:0.375) (0.375:0.375:0.375))
        (PORT datab (0.543:0.543:0.543) (0.543:0.543:0.543))
        (PORT datad (0.603:0.603:0.603) (0.603:0.603:0.603))
        (IOPATH dataa combout (0.541:0.541:0.541) (0.541:0.541:0.541))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datac combout (0.358:0.358:0.358) (0.358:0.358:0.358))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter_ffa\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.716:1.716:1.716) (1.716:1.716:1.716))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.71:1.71:1.71) (1.71:1.71:1.71))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[1\]\~feeder)
    (DELAY
      (ABSOLUTE
        (PORT datad (0.937:0.937:0.937) (0.937:0.937:0.937))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (PORT ena (1.611:1.611:1.611) (1.611:1.611:1.611))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
      (HOLD ena (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|countera6)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.403:0.403:0.403) (0.403:0.403:0.403))
        (PORT datab (0.389:0.389:0.389) (0.389:0.389:0.389))
        (IOPATH dataa combout (0.545:0.545:0.545) (0.545:0.545:0.545))
        (IOPATH dataa cout (0.517:0.517:0.517) (0.517:0.517:0.517))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
        (IOPATH cin combout (0.458:0.458:0.458) (0.458:0.458:0.458))
        (IOPATH cin cout (0.08:0.08:0.08) (0.08:0.08:0.08))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|countera7)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.411:0.411:0.411) (0.411:0.411:0.411))
        (PORT datab (0.389:0.389:0.389) (0.389:0.389:0.389))
        (IOPATH dataa combout (0.542:0.542:0.542) (0.542:0.542:0.542))
        (IOPATH datab combout (0.491:0.491:0.491) (0.491:0.491:0.491))
        (IOPATH datab cout (0.495:0.495:0.495) (0.495:0.495:0.495))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
        (IOPATH cin combout (0.458:0.458:0.458) (0.458:0.458:0.458))
        (IOPATH cin cout (0.08:0.08:0.08) (0.08:0.08:0.08))
      )
    )