asyn_fifo_v.sdo

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输

// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP2C35F672C7 Package FBGA672
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "asyn_fifo")
  (DATE "08/28/2008 17:14:40")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 8.0 Build 215 05/29/2008 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ns)

  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrptr_gp\|parity)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.597:0.597:0.597) (0.597:0.597:0.597))
        (PORT datab (0.315:0.315:0.315) (0.315:0.315:0.315))
        (IOPATH dataa combout (0.544:0.544:0.544) (0.544:0.544:0.544))
        (IOPATH dataa cout (0.517:0.517:0.517) (0.517:0.517:0.517))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datab cout (0.495:0.495:0.495) (0.495:0.495:0.495))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.383:0.383:0.383) (0.383:0.383:0.383))
        (PORT datab (0.313:0.313:0.313) (0.313:0.313:0.313))
        (IOPATH dataa combout (0.544:0.544:0.544) (0.544:0.544:0.544))
        (IOPATH dataa cout (0.517:0.517:0.517) (0.517:0.517:0.517))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datab cout (0.495:0.495:0.495) (0.495:0.495:0.495))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|p0addr)
    (DELAY
      (ABSOLUTE
        (PORT clk (1.712:1.712:1.712) (1.712:1.712:1.712))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.706:1.706:1.706) (1.706:1.706:1.706))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.711:1.711:1.711) (1.711:1.711:1.711))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.711:1.711:1.711) (1.711:1.711:1.711))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.716:1.716:1.716) (1.716:1.716:1.716))
        (PORT sdata (0.778:0.778:0.778) (0.778:0.778:0.778))
        (PORT aclr (1.719:1.719:1.719) (1.719:1.719:1.719))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.716:1.716:1.716) (1.716:1.716:1.716))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.719:1.719:1.719) (1.719:1.719:1.719))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rdempty_eq_comp_aeb_int\~87)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.38:0.38:0.38) (0.38:0.38:0.38))
        (PORT datab (0.599:0.599:0.599) (0.599:0.599:0.599))
        (PORT datad (0.36:0.36:0.36) (0.36:0.36:0.36))
        (IOPATH dataa combout (0.541:0.541:0.541) (0.541:0.541:0.541))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datac combout (0.358:0.358:0.358) (0.358:0.358:0.358))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe10a\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.716:1.716:1.716) (1.716:1.716:1.716))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.719:1.719:1.719) (1.719:1.719:1.719))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut1\|state\.WRITE)
    (DELAY
      (ABSOLUTE
        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe11\|dffe13a\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe11\|dffe13a\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT sdata (0.776:0.776:0.776) (0.776:0.776:0.776))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|wrfull_eq_comp_aeb_int\~84)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.379:0.379:0.379) (0.379:0.379:0.379))
        (PORT datab (0.607:0.607:0.607) (0.607:0.607:0.607))
        (PORT datad (0.612:0.612:0.612) (0.612:0.612:0.612))
        (IOPATH dataa combout (0.544:0.544:0.544) (0.544:0.544:0.544))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datac combout (0.358:0.358:0.358) (0.358:0.358:0.358))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[11\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.711:1.711:1.711) (1.711:1.711:1.711))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.711:1.711:1.711) (1.711:1.711:1.711))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.714:1.714:1.714) (1.714:1.714:1.714))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.716:1.716:1.716) (1.716:1.716:1.716))
        (PORT sdata (1.299:1.299:1.299) (1.299:1.299:1.299))
        (PORT aclr (1.719:1.719:1.719) (1.719:1.719:1.719))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[4\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.716:1.716:1.716) (1.716:1.716:1.716))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.719:1.719:1.719) (1.719:1.719:1.719))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe8\|dffe9a\[2\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.709:1.709:1.709) (1.709:1.709:1.709))
        (PORT sdata (1.3:1.3:1.3) (1.3:1.3:1.3))
        (PORT aclr (1.712:1.712:1.712) (1.712:1.712:1.712))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (0.286:0.286:0.286))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE dut1\|always1\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (0.32:0.32:0.32) (0.32:0.32:0.32))
        (PORT datab (0.812:0.812:0.812) (0.812:0.812:0.812))
        (PORT datac (6.228:6.228:6.228) (6.228:6.228:6.228))
        (PORT datad (0.824:0.824:0.824) (0.824:0.824:0.824))
        (IOPATH dataa combout (0.545:0.545:0.545) (0.545:0.545:0.545))
        (IOPATH datab combout (0.521:0.521:0.521) (0.521:0.521:0.521))
        (IOPATH datac combout (0.322:0.322:0.322) (0.322:0.322:0.322))
        (IOPATH datad combout (0.178:0.178:0.178) (0.178:0.178:0.178))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE dut0\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe11\|dffe12a\[6\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1.714:1.714:1.714) (1.714:1.714:1.714))
        (PORT datain (0.096:0.096:0.096) (0.096:0.096:0.096))
        (PORT aclr (1.715:1.715:1.715) (1.715:1.715:1.715))
        (IOPATH (posedge clk) regout (0.277:0.277:0.277) (0.277:0.277:0.277))
        (IOPATH (posedge aclr) regout (0.243:0.243:0.243) (0.243:0.243:0.243))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (0.286:0.286:0.286))
    )