asyn_fifo_modelsim.xrf

FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输

vendor_name = ModelSim
source_file = 1, D:/design/asynch_fifo/read_control_logic.v
source_file = 1, D:/design/asynch_fifo/dcfifo0.qip
source_file = 1, D:/design/asynch_fifo/dcfifo0.v
source_file = 1, D:/design/asynch_fifo/asyn_fifo.v
source_file = 1, D:/design/asynch_fifo/write_control_logic.v
source_file = 1, D:/design/asynch_fifo/Waveform1.vwf
source_file = 1, D:/design/asynch_fifo/db/asyn_fifo.cbx.xml
source_file = 1, f:/altera/quartus/libraries/megafunctions/dcfifo.tdf
source_file = 1, f:/altera/quartus/libraries/megafunctions/lpm_counter.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/lpm_add_sub.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/altdpram.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/a_graycounter.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/a_fefifo.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/a_gray2bin.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/dffpipe.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/alt_sync_fifo.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/lpm_compare.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/altsyncram_fifo.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/aglobal80.inc
source_file = 1, f:/altera/quartus/libraries/megafunctions/cbx.lst
source_file = 1, D:/design/asynch_fifo/db/dcfifo_10i1.tdf
source_file = 1, D:/design/asynch_fifo/db/a_graycounter_q96.tdf
source_file = 1, D:/design/asynch_fifo/db/a_graycounter_hgc.tdf
source_file = 1, D:/design/asynch_fifo/db/a_graycounter_ggc.tdf
source_file = 1, D:/design/asynch_fifo/db/altsyncram_to61.tdf
source_file = 1, D:/design/asynch_fifo/db/altsyncram_9ve1.tdf
source_file = 1, D:/design/asynch_fifo/db/dffpipe_ngh.tdf
source_file = 1, D:/design/asynch_fifo/db/alt_synch_pipe_tdb.tdf
source_file = 1, D:/design/asynch_fifo/db/dffpipe_re9.tdf
source_file = 1, D:/design/asynch_fifo/db/alt_synch_pipe_1e8.tdf
source_file = 1, D:/design/asynch_fifo/db/dffpipe_se9.tdf
design_name = asyn_fifo
instance = comp, \dut0|dcfifo_component|auto_generated|wrptr_gp|parity , dut0|dcfifo_component|auto_generated|wrptr_gp|parity, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity , dut0|dcfifo_component|auto_generated|rdptr_g1p|parity, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|p0addr , dut0|dcfifo_component|auto_generated|p0addr, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[11] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[11], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[1] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[1], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[3] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[3], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[4] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[4], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~87 , dut0|dcfifo_component|auto_generated|rdempty_eq_comp_aeb_int~87, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[2] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[2], asyn_fifo, 1
instance = comp, \dut1|state.WRITE , dut1|state.WRITE, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[6] , dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[6], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[11] , dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[11], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~84 , dut0|dcfifo_component|auto_generated|wrfull_eq_comp_aeb_int~84, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[11] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[11], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[1] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[1], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[3] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[3], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[4] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[4], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[2] , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[2], asyn_fifo, 1
instance = comp, \dut1|always1~0 , dut1|always1~0, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[6] , dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[6], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|wrptr_gp|parity_ff , dut0|dcfifo_component|auto_generated|wrptr_gp|parity_ff, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[11] , dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[11], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rdptr_g1p|parity_ff , dut0|dcfifo_component|auto_generated|rdptr_g1p|parity_ff, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[11] , dut0|dcfifo_component|auto_generated|delayed_wrptr_g[11], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[1] , dut0|dcfifo_component|auto_generated|delayed_wrptr_g[1], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[3] , dut0|dcfifo_component|auto_generated|delayed_wrptr_g[3], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[4] , dut0|dcfifo_component|auto_generated|delayed_wrptr_g[4], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[2] , dut0|dcfifo_component|auto_generated|delayed_wrptr_g[2], asyn_fifo, 1
instance = comp, \iDVAL~I , iDVAL, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[6]~feeder , dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe12a[6]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder , dut0|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[3]~feeder , dut0|dcfifo_component|auto_generated|delayed_wrptr_g[3]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder , dut0|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[11]~feeder , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[11]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[1]~feeder , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[1]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[4]~feeder , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[4]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[2]~feeder , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe10a[2]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[6]~feeder , dut0|dcfifo_component|auto_generated|ws_dgrp|dffpipe11|dffe13a[6]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[11]~feeder , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[11]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[1]~feeder , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[1]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[4]~feeder , dut0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8|dffe9a[4]~feeder, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|p0addr~feeder , dut0|dcfifo_component|auto_generated|p0addr~feeder, asyn_fifo, 1
instance = comp, \iCLK2~I , iCLK2, asyn_fifo, 1
instance = comp, \iCLK2~clkctrl , iCLK2~clkctrl, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera0 , dut0|dcfifo_component|auto_generated|rdptr_g1p|countera0, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera1 , dut0|dcfifo_component|auto_generated|rdptr_g1p|countera1, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rdptr_g1p|countera2 , dut0|dcfifo_component|auto_generated|rdptr_g1p|countera2, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~feeder , dut0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~feeder, asyn_fifo, 1
instance = comp, \iRST~I , iRST, asyn_fifo, 1
instance = comp, \iRST~clkctrl , iRST~clkctrl, asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rdaclr|dffe7a[0] , dut0|dcfifo_component|auto_generated|rdaclr|dffe7a[0], asyn_fifo, 1
instance = comp, \dut0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~clkctrl , dut0|dcfifo_component|auto_generated|rdaclr|dffe7a[0]~clkctrl, asyn_fifo, 1