coregen.log

使用VHDL编程的异步FIFO程序 经调试可运行

# Xilinx CORE Generator 6.1i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in C:\Xilinx\bin\fifo\coregen.log
NEWPROJECT .
SETPROJECT .
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=C:\Xilinx\bin\fifo
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=C:\Xilinx\bin\fifo
Set current Project to C:\Xilinx\bin\fifo
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1841
XIPCPJSENDCORES spartan3