fifo.npl

来自「使用VHDL编程的异步FIFO程序 经调试可运行」· NPL 代码 · 共 30 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT fifo
DESIGN fifo
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE fifo2.v
SOURCE fifomem2.v
SOURCE async_cmp.v
SOURCE rptr_empty2.v
SOURCE wptr_full2.v
[STATUS-ALL]
fifo2.ngcFile=WARNINGS,1217652979
[STRATEGY-LIST]
Normal=True