fifo2.twr

使用VHDL编程的异步FIFO程序 经调试可运行

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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml fifo2 fifo2.ncd -o
fifo2.twr fifo2.pcf


Design file:              fifo2.ncd
Physical constraint file: fifo2.pcf
Device,speed:             xc3s200,-4 (PREVIEW 1.26 2003-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock rclk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
rinc        |    1.894(R)|    0.352(R)|rclk_BUFGP        |   0.000|
wrst_n      |    1.990(R)|   -0.587(R)|rclk_BUFGP        |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock wclk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
wdata<0>    |    0.394(R)|    0.707(R)|wclk_BUFGP        |   0.000|
wdata<1>    |    0.675(R)|    0.473(R)|wclk_BUFGP        |   0.000|
wdata<2>    |    1.289(R)|   -0.011(R)|wclk_BUFGP        |   0.000|
wdata<3>    |    0.662(R)|    0.483(R)|wclk_BUFGP        |   0.000|
wdata<4>    |    1.199(R)|    0.055(R)|wclk_BUFGP        |   0.000|
wdata<5>    |    0.669(R)|    0.477(R)|wclk_BUFGP        |   0.000|
wdata<6>    |    0.667(R)|    0.477(R)|wclk_BUFGP        |   0.000|
wdata<7>    |    0.413(R)|    0.684(R)|wclk_BUFGP        |   0.000|
winc        |    3.001(R)|    0.431(R)|wclk_BUFGP        |   0.000|
wrst_n      |    3.905(R)|   -2.118(R)|wclk_BUFGP        |   0.000|
------------+------------+------------+------------------+--------+

Clock rclk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
rdata<0>    |   11.150(R)|rclk_BUFGP        |   0.000|
rdata<1>    |   11.452(R)|rclk_BUFGP        |   0.000|
rdata<2>    |   11.188(R)|rclk_BUFGP        |   0.000|
rdata<3>    |   10.824(R)|rclk_BUFGP        |   0.000|
rdata<4>    |   11.419(R)|rclk_BUFGP        |   0.000|
rdata<5>    |   11.452(R)|rclk_BUFGP        |   0.000|
rdata<6>    |   11.763(R)|rclk_BUFGP        |   0.000|
rdata<7>    |   11.353(R)|rclk_BUFGP        |   0.000|
rempty      |    9.900(R)|rclk_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock wclk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
rdata<0>    |   10.372(R)|wclk_BUFGP        |   0.000|
rdata<1>    |   10.606(R)|wclk_BUFGP        |   0.000|
rdata<2>    |   10.907(R)|wclk_BUFGP        |   0.000|
rdata<3>    |   10.535(R)|wclk_BUFGP        |   0.000|
rdata<4>    |   10.878(R)|wclk_BUFGP        |   0.000|
rdata<5>    |   10.606(R)|wclk_BUFGP        |   0.000|
rdata<6>    |   11.166(R)|wclk_BUFGP        |   0.000|
rdata<7>    |   10.812(R)|wclk_BUFGP        |   0.000|
wfull       |    9.611(R)|wclk_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock rclk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
rclk           |    4.710|         |         |         |
wclk           |    4.767|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock wclk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
rclk           |    4.826|         |         |         |
wclk           |    4.596|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sat Aug 02 12:56:25 2008
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Peak Memory Usage: 54 MB