fifo2.v

使用VHDL编程的异步FIFO程序 经调试可运行

module fifo2 (rdata, wfull, rempty, wdata, 
winc, wclk, wrst_n, rinc, rclk, rrst_n); 
parameter DSIZE = 8; 
parameter ASIZE = 4; 
output [DSIZE-1:0] rdata; 
output wfull; 
output rempty; 
input [DSIZE-1:0] wdata; 
input winc, wclk, wrst_n; 
input rinc, rclk, rrst_n; 
wire [ASIZE-1:0] wptr, rptr; 
wire [ASIZE-1:0] waddr, raddr; 

async_cmp #(ASIZE) async_cmp(.aempty_n(aempty_n), 
.afull_n(afull_n), 
.wptr(wptr), .rptr(rptr), 
.wrst_n(wrst_n)); 

fifomem2 #(DSIZE, ASIZE) fifomem2(.rdata(rdata), 
.wdata(wdata), 
.waddr(wptr), 
.raddr(rptr), 
.wclken(winc), 
.wclk(wclk)); 

rptr_empty2 #(ASIZE) rptr_empty2(.rempty(rempty), 
.rptr(rptr), 
.aempty_n(aempty_n), 
.rinc(rinc), 
.rclk(rclk), 
.rrst_n(rrst_n)); 

wptr_full2 #(ASIZE) wptr_full2(.wfull(wfull), 
.wptr(wptr), 
.afull_n(afull_n), 
.winc(winc), 
.wclk(wclk), 
.wrst_n(wrst_n)); 
endmodule