config_dac.tan.rpt
来自「Verilog实现 spi接口的FPGA实现 通过仿真」· RPT 代码 · 共 363 行 · 第 1/5 页
RPT
363 行
; N/A ; 417.01 MHz ( period = 2.398 ns ) ; bit_transfered[0] ; data_to_send[2] ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; 417.01 MHz ( period = 2.398 ns ) ; bit_transfered[0] ; data_to_send[1] ; clk ; clk ; None ; None ; 2.184 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; rd_data[0]~reg0 ; clk ; clk ; None ; None ; 2.143 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; rd_data[1]~reg0 ; clk ; clk ; None ; None ; 2.143 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; rd_data[2]~reg0 ; clk ; clk ; None ; None ; 2.143 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; rd_data[3]~reg0 ; clk ; clk ; None ; None ; 2.143 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; rd_data[4]~reg0 ; clk ; clk ; None ; None ; 2.143 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; rd_data[5]~reg0 ; clk ; clk ; None ; None ; 2.143 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; rd_data[6]~reg0 ; clk ; clk ; None ; None ; 2.143 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; rd_data[7]~reg0 ; clk ; clk ; None ; None ; 2.143 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; bit_transfered[0] ; clk ; clk ; None ; None ; 2.119 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; bit_transfered[8] ; clk ; clk ; None ; None ; 2.119 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; bit_transfered[7] ; clk ; clk ; None ; None ; 2.119 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; bit_transfered[1] ; clk ; clk ; None ; None ; 2.119 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.DATA ; data_to_send[7] ; clk ; clk ; None ; None ; 2.080 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.DATA ; data_to_send[6] ; clk ; clk ; None ; None ; 2.080 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.DATA ; data_to_send[5] ; clk ; clk ; None ; None ; 2.080 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.DATA ; data_to_send[4] ; clk ; clk ; None ; None ; 2.080 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.DATA ; data_to_send[3] ; clk ; clk ; None ; None ; 2.080 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.DATA ; data_to_send[2] ; clk ; clk ; None ; None ; 2.080 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.DATA ; data_to_send[1] ; clk ; clk ; None ; None ; 2.080 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.INSTRUCTION ; data_to_send[0] ; clk ; clk ; None ; None ; 1.970 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.DATA ; data_to_send[0] ; clk ; clk ; None ; None ; 1.942 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; bit_transfered[0] ; data_to_send[0] ; clk ; clk ; None ; None ; 1.918 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.START ; bit_transfered[0] ; clk ; clk ; None ; None ; 1.915 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.START ; bit_transfered[8] ; clk ; clk ; None ; None ; 1.915 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.START ; bit_transfered[7] ; clk ; clk ; None ; None ; 1.915 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.START ; bit_transfered[1] ; clk ; clk ; None ; None ; 1.915 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; spi_ncs~reg0 ; clk ; clk ; None ; None ; 1.904 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; data_received[0] ; clk ; clk ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; data_received[1] ; clk ; clk ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; data_received[2] ; clk ; clk ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; data_received[3] ; clk ; clk ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; data_received[4] ; clk ; clk ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; data_received[5] ; clk ; clk ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; data_received[6] ; clk ; clk ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; data_received[7] ; clk ; clk ; None ; None ; 1.873 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; bit_transfered[0] ; clk ; clk ; None ; None ; 1.835 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; bit_transfered[8] ; clk ; clk ; None ; None ; 1.835 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; bit_transfered[7] ; clk ; clk ; None ; None ; 1.835 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; bit_transfered[1] ; clk ; clk ; None ; None ; 1.835 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.IDLE ; bit_transfered[0] ; clk ; clk ; None ; None ; 1.801 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.IDLE ; bit_transfered[8] ; clk ; clk ; None ; None ; 1.801 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.IDLE ; bit_transfered[7] ; clk ; clk ; None ; None ; 1.801 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.IDLE ; bit_transfered[1] ; clk ; clk ; None ; None ; 1.801 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; bit_transfered[8] ; data_to_send[7] ; clk ; clk ; None ; None ; 1.791 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; bit_transfered[8] ; data_to_send[6] ; clk ; clk ; None ; None ; 1.791 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; bit_transfered[8] ; data_to_send[5] ; clk ; clk ; None ; None ; 1.791 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; bit_transfered[8] ; data_to_send[4] ; clk ; clk ; None ; None ; 1.791 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; bit_transfered[8] ; data_to_send[3] ; clk ; clk ; None ; None ; 1.791 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; bit_transfered[8] ; data_to_send[2] ; clk ; clk ; None ; None ; 1.791 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; bit_transfered[8] ; data_to_send[1] ; clk ; clk ; None ; None ; 1.791 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_to_send[0] ; clk ; clk ; None ; None ; 1.749 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[0] ; spi_ncs~reg0 ; clk ; clk ; None ; None ; 1.743 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_received[0] ; clk ; clk ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_received[1] ; clk ; clk ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_received[2] ; clk ; clk ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_received[3] ; clk ; clk ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_received[4] ; clk ; clk ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_received[5] ; clk ; clk ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_received[6] ; clk ; clk ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_received[7] ; clk ; clk ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; main_state.DATA ; clk ; clk ; None ; None ; 1.716 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; waddr[3] ; data_to_send[3] ; clk ; clk ; None ; None ; 1.687 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_to_send[7] ; clk ; clk ; None ; None ; 1.681 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_to_send[6] ; clk ; clk ; None ; None ; 1.681 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_to_send[5] ; clk ; clk ; None ; None ; 1.681 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_to_send[4] ; clk ; clk ; None ; None ; 1.681 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_to_send[3] ; clk ; clk ; None ; None ; 1.681 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_to_send[2] ; clk ; clk ; None ; None ; 1.681 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sck_count[1] ; data_to_send[1] ; clk ; clk ; None ; None ; 1.681 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; bit_transfered[8] ; data_to_send[0] ; clk ; clk ; None ; None ; 1.653 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; main_state.DATA ; rd_data[0]~reg0 ; clk ; clk ; None ; None ; 1.633 ns ;
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