_primary.vhd

来自「Verilog实现 spi接口的FPGA实现 通过仿真」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity ad9777_spi_interface is
    port(
        spi_ncs         : in     vl_logic;
        spi_sck         : in     vl_logic;
        spi_sdio        : in     vl_logic;
        spi_sdo         : out    vl_logic
    );
end ad9777_spi_interface;