counter4x5.tan.qmsg

完成的是RS422信号的计数功能

{ "Info" "ITDB_FULL_TCO_RESULT" "Clock SEG\[5\] SEGCtr:inst5\|oDIG\[0\] 37.000 ns register " "Info: tco from clock \"Clock\" to destination pin \"SEG\[5\]\" through register \"SEGCtr:inst5\|oDIG\[0\]\" is 37.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 9.500 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to source register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clock 1 CLK PIN_83 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 65; CLK Node = 'Clock'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { Clock } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -304 -192 -24 -288 "Clock" "" } { -120 552 1088 -104 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns CLOCK:inst7\|CLK2 2 REG LC36 19 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC36; Fanout = 19; REG Node = 'CLOCK:inst7\|CLK2'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "2.000 ns" { Clock CLOCK:inst7|CLK2 } "NODE_NAME" } "" } } { "CLOCK.v" "" { Text "E:/job/DelayTrigIndex/CLOCK.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns SEGCtr:inst5\|oDIG\[0\] 3 REG LC89 25 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC89; Fanout = 25; REG Node = 'SEGCtr:inst5\|oDIG\[0\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.000 ns" { CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "SEGCtr.v" "" { Text "E:/job/DelayTrigIndex/SEGCtr.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns 89.47 % " "Info: Total cell delay = 8.500 ns ( 89.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.53 % " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "9.500 ns" { Clock CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { Clock Clock~out CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "SEGCtr.v" "" { Text "E:/job/DelayTrigIndex/SEGCtr.v" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "25.500 ns + Longest register pin " "Info: + Longest register to pin delay is 25.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SEGCtr:inst5\|oDIG\[0\] 1 REG LC89 25 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC89; Fanout = 25; REG Node = 'SEGCtr:inst5\|oDIG\[0\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "SEGCtr.v" "" { Text "E:/job/DelayTrigIndex/SEGCtr.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns SEG7_LUT:inst6\|oSEG~202 2 COMB LC98 5 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC98; Fanout = 5; COMB Node = 'SEG7_LUT:inst6\|oSEG~202'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "8.000 ns" { SEGCtr:inst5|oDIG[0] SEG7_LUT:inst6|oSEG~202 } "NODE_NAME" } "" } } { "SEG7_LUT.v" "" { Text "E:/job/DelayTrigIndex/SEG7_LUT.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 16.000 ns SEG7_LUT:inst6\|reduce_or~474sexpbal 3 COMB LC51 3 " "Info: 3: + IC(1.000 ns) + CELL(7.000 ns) = 16.000 ns; Loc. = LC51; Fanout = 3; COMB Node = 'SEG7_LUT:inst6\|reduce_or~474sexpbal'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "8.000 ns" { SEG7_LUT:inst6|oSEG~202 SEG7_LUT:inst6|reduce_or~474sexpbal } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 24.000 ns SEG7_LUT:inst6\|oSEG\[5\]~239 4 COMB LOOP LC67 3 " "Info: 4: + IC(0.000 ns) + CELL(8.000 ns) = 24.000 ns; Loc. = LC67; Fanout = 3; COMB LOOP Node = 'SEG7_LUT:inst6\|oSEG\[5\]~239'" { { "Info" "ITDB_PART_OF_SCC" "SEG7_LUT:inst6\|oSEG\[5\]~239 LC67 " "Info: Loc. = LC67; Node \"SEG7_LUT:inst6\|oSEG\[5\]~239\"" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { SEG7_LUT:inst6|oSEG[5]~239 } "NODE_NAME" } "" } }  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { SEG7_LUT:inst6|oSEG[5]~239 } "NODE_NAME" } "" } } { "SEG7_LUT.v" "" { Text "E:/job/DelayTrigIndex/SEG7_LUT.v" 3 -1 0 } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "8.000 ns" { SEG7_LUT:inst6|reduce_or~474sexpbal SEG7_LUT:inst6|oSEG[5]~239 } "NODE_NAME" } "" } } { "SEG7_LUT.v" "" { Text "E:/job/DelayTrigIndex/SEG7_LUT.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 25.500 ns SEG\[5\] 5 PIN PIN_45 0 " "Info: 5: + IC(0.000 ns) + CELL(1.500 ns) = 25.500 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'SEG\[5\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { SEG7_LUT:inst6|oSEG[5]~239 SEG[5] } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { 88 1824 2000 104 "SEG\[6..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.500 ns 92.16 % " "Info: Total cell delay = 23.500 ns ( 92.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 7.84 % " "Info: Total interconnect delay = 2.000 ns ( 7.84 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "25.500 ns" { SEGCtr:inst5|oDIG[0] SEG7_LUT:inst6|oSEG~202 SEG7_LUT:inst6|reduce_or~474sexpbal SEG7_LUT:inst6|oSEG[5]~239 SEG[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.500 ns" { SEGCtr:inst5|oDIG[0] SEG7_LUT:inst6|oSEG~202 SEG7_LUT:inst6|reduce_or~474sexpbal SEG7_LUT:inst6|oSEG[5]~239 SEG[5] } { 0.000ns 1.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 7.000ns 7.000ns 8.000ns 1.500ns } } }  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "9.500 ns" { Clock CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { Clock Clock~out CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } { 0.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns } } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "25.500 ns" { SEGCtr:inst5|oDIG[0] SEG7_LUT:inst6|oSEG~202 SEG7_LUT:inst6|reduce_or~474sexpbal SEG7_LUT:inst6|oSEG[5]~239 SEG[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.500 ns" { SEGCtr:inst5|oDIG[0] SEG7_LUT:inst6|oSEG~202 SEG7_LUT:inst6|reduce_or~474sexpbal SEG7_LUT:inst6|oSEG[5]~239 SEG[5] } { 0.000ns 1.000ns 1.000ns 0.000ns 0.000ns } { 0.000ns 7.000ns 7.000ns 8.000ns 1.500ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "SEL:inst4\|Step\[5\] SW\[0\] Clock -2.000 ns register " "Info: th for register \"SEL:inst4\|Step\[5\]\" (data pin = \"SW\[0\]\", clock pin = \"Clock\") is -2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clock 1 CLK PIN_83 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 65; CLK Node = 'Clock'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { Clock } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -304 -192 -24 -288 "Clock" "" } { -120 552 1088 -104 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns SEL:inst4\|Step\[5\] 2 REG LC22 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC22; Fanout = 1; REG Node = 'SEL:inst4\|Step\[5\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "0.000 ns" { Clock SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "SEL.v" "" { Text "E:/job/DelayTrigIndex/SEL.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out SEL:inst4|Step[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "SEL.v" "" { Text "E:/job/DelayTrigIndex/SEL.v" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SW\[0\] 1 PIN PIN_74 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_74; Fanout = 4; PIN Node = 'SW\[0\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { SW[0] } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { 120 752 920 136 "SW\[2..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns SEL:inst4\|Step\[5\] 2 REG LC22 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC22; Fanout = 1; REG Node = 'SEL:inst4\|Step\[5\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.000 ns" { SW[0] SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "SEL.v" "" { Text "E:/job/DelayTrigIndex/SEL.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.500 ns" { SW[0] SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { SW[0] SW[0]~out SEL:inst4|Step[5] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out SEL:inst4|Step[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.500 ns" { SW[0] SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { SW[0] SW[0]~out SEL:inst4|Step[5] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 28 18:27:44 2008 " "Info: Processing ended: Wed May 28 18:27:44 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}