counter4x5.tan.qmsg

完成的是RS422信号的计数功能

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock " "Info: Assuming node \"Clock\" is an undefined clock" {  } { { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -304 -192 -24 -288 "Clock" "" } { -120 552 1088 -104 "Clock" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Clock" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLOCK:inst7\|CLK2 " "Info: Detected ripple clock \"CLOCK:inst7\|CLK2\" as buffer" {  } { { "CLOCK.v" "" { Text "E:/job/DelayTrigIndex/CLOCK.v" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLOCK:inst7\|CLK2" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock register JA0 register Decoder:inst9\|CntTe\[23\] 53.19 MHz 18.8 ns Internal " "Info: Clock \"Clock\" has Internal fmax of 53.19 MHz between source register \"JA0\" and destination register \"Decoder:inst9\|CntTe\[23\]\" (period= 18.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.800 ns + Longest register register " "Info: + Longest register to register delay is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns JA0 1 REG LC78 64 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC78; Fanout = 64; REG Node = 'JA0'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { JA0 } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -432 568 632 -352 "JA0" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns Decoder:inst9\|TrigTe~117 2 COMB LC123 56 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC123; Fanout = 56; COMB Node = 'Decoder:inst9\|TrigTe~117'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "8.000 ns" { JA0 Decoder:inst9|TrigTe~117 } "NODE_NAME" } "" } } { "Decoder.v" "" { Text "E:/job/DelayTrigIndex/Decoder.v" 44 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 14.000 ns Decoder:inst9\|CntTe~5365 3 COMB LC7 1 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 14.000 ns; Loc. = LC7; Fanout = 1; COMB Node = 'Decoder:inst9\|CntTe~5365'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.000 ns" { Decoder:inst9|TrigTe~117 Decoder:inst9|CntTe~5365 } "NODE_NAME" } "" } } { "Decoder.v" "" { Text "E:/job/DelayTrigIndex/Decoder.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 14.800 ns Decoder:inst9\|CntTe\[23\] 4 REG LC8 11 " "Info: 4: + IC(0.000 ns) + CELL(0.800 ns) = 14.800 ns; Loc. = LC8; Fanout = 11; REG Node = 'Decoder:inst9\|CntTe\[23\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "0.800 ns" { Decoder:inst9|CntTe~5365 Decoder:inst9|CntTe[23] } "NODE_NAME" } "" } } { "Decoder.v" "" { Text "E:/job/DelayTrigIndex/Decoder.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.800 ns 86.49 % " "Info: Total cell delay = 12.800 ns ( 86.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 13.51 % " "Info: Total interconnect delay = 2.000 ns ( 13.51 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "14.800 ns" { JA0 Decoder:inst9|TrigTe~117 Decoder:inst9|CntTe~5365 Decoder:inst9|CntTe[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.800 ns" { JA0 Decoder:inst9|TrigTe~117 Decoder:inst9|CntTe~5365 Decoder:inst9|CntTe[23] } { 0.000ns 1.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 5.000ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clock 1 CLK PIN_83 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 65; CLK Node = 'Clock'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { Clock } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -304 -192 -24 -288 "Clock" "" } { -120 552 1088 -104 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns Decoder:inst9\|CntTe\[23\] 2 REG LC8 11 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC8; Fanout = 11; REG Node = 'Decoder:inst9\|CntTe\[23\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "0.000 ns" { Clock Decoder:inst9|CntTe[23] } "NODE_NAME" } "" } } { "Decoder.v" "" { Text "E:/job/DelayTrigIndex/Decoder.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock Decoder:inst9|CntTe[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out Decoder:inst9|CntTe[23] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"Clock\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clock 1 CLK PIN_83 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 65; CLK Node = 'Clock'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { Clock } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -304 -192 -24 -288 "Clock" "" } { -120 552 1088 -104 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns JA0 2 REG LC78 64 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC78; Fanout = 64; REG Node = 'JA0'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "0.000 ns" { Clock JA0 } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -432 568 632 -352 "JA0" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock JA0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out JA0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock Decoder:inst9|CntTe[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out Decoder:inst9|CntTe[23] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock JA0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out JA0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -432 568 632 -352 "JA0" "" } } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "Decoder.v" "" { Text "E:/job/DelayTrigIndex/Decoder.v" 47 -1 0 } }  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "14.800 ns" { JA0 Decoder:inst9|TrigTe~117 Decoder:inst9|CntTe~5365 Decoder:inst9|CntTe[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.800 ns" { JA0 Decoder:inst9|TrigTe~117 Decoder:inst9|CntTe~5365 Decoder:inst9|CntTe[23] } { 0.000ns 1.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 5.000ns 0.800ns } } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock Decoder:inst9|CntTe[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out Decoder:inst9|CntTe[23] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock JA0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out JA0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "Clock 24 " "Warning: Circuit may not operate. Detected 24 non-operational path(s) clocked by clock \"Clock\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "Decoder:inst9\|CntTe\[20\] SEGCtr:inst5\|oDIG\[0\] Clock 3.0 ns " "Info: Found hold time violation between source  pin or register \"Decoder:inst9\|CntTe\[20\]\" and destination pin or register \"SEGCtr:inst5\|oDIG\[0\]\" for clock \"Clock\" (Hold time is 3.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "8.000 ns + Largest " "Info: + Largest clock skew is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 9.500 ns + Longest register " "Info: + Longest clock path from clock \"Clock\" to destination register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clock 1 CLK PIN_83 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 65; CLK Node = 'Clock'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { Clock } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -304 -192 -24 -288 "Clock" "" } { -120 552 1088 -104 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns CLOCK:inst7\|CLK2 2 REG LC36 19 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC36; Fanout = 19; REG Node = 'CLOCK:inst7\|CLK2'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "2.000 ns" { Clock CLOCK:inst7|CLK2 } "NODE_NAME" } "" } } { "CLOCK.v" "" { Text "E:/job/DelayTrigIndex/CLOCK.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns SEGCtr:inst5\|oDIG\[0\] 3 REG LC89 25 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = LC89; Fanout = 25; REG Node = 'SEGCtr:inst5\|oDIG\[0\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.000 ns" { CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "SEGCtr.v" "" { Text "E:/job/DelayTrigIndex/SEGCtr.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns 89.47 % " "Info: Total cell delay = 8.500 ns ( 89.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.53 % " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "9.500 ns" { Clock CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { Clock Clock~out CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } { 0.0ns 0.0ns 0.0ns 1.0ns } { 0.0ns 1.5ns 2.0ns 5.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clock 1 CLK PIN_83 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 65; CLK Node = 'Clock'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { Clock } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -304 -192 -24 -288 "Clock" "" } { -120 552 1088 -104 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns Decoder:inst9\|CntTe\[20\] 2 REG LC2 21 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 21; REG Node = 'Decoder:inst9\|CntTe\[20\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "0.000 ns" { Clock Decoder:inst9|CntTe[20] } "NODE_NAME" } "" } } { "Decoder.v" "" { Text "E:/job/DelayTrigIndex/Decoder.v" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock Decoder:inst9|CntTe[20] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out Decoder:inst9|CntTe[20] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } }  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "9.500 ns" { Clock CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { Clock Clock~out CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } { 0.0ns 0.0ns 0.0ns 1.0ns } { 0.0ns 1.5ns 2.0ns 5.0ns } } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock Decoder:inst9|CntTe[20] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out Decoder:inst9|CntTe[20] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns - " "Info: - Micro clock to output delay of source is 2.000 ns" {  } { { "Decoder.v" "" { Text "E:/job/DelayTrigIndex/Decoder.v" 47 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns - Shortest register register " "Info: - Shortest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Decoder:inst9\|CntTe\[20\] 1 REG LC2 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 21; REG Node = 'Decoder:inst9\|CntTe\[20\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { Decoder:inst9|CntTe[20] } "NODE_NAME" } "" } } { "Decoder.v" "" { Text "E:/job/DelayTrigIndex/Decoder.v" 47 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns SEGCtr:inst5\|oDIG\[0\] 2 REG LC89 25 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC89; Fanout = 25; REG Node = 'SEGCtr:inst5\|oDIG\[0\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.000 ns" { Decoder:inst9|CntTe[20] SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "SEGCtr.v" "" { Text "E:/job/DelayTrigIndex/SEGCtr.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns 83.33 % " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 16.67 % " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.000 ns" { Decoder:inst9|CntTe[20] SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { Decoder:inst9|CntTe[20] SEGCtr:inst5|oDIG[0] } { 0.0ns 1.0ns } { 0.0ns 5.0ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "SEGCtr.v" "" { Text "E:/job/DelayTrigIndex/SEGCtr.v" 12 -1 0 } }  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "9.500 ns" { Clock CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.500 ns" { Clock Clock~out CLOCK:inst7|CLK2 SEGCtr:inst5|oDIG[0] } { 0.0ns 0.0ns 0.0ns 1.0ns } { 0.0ns 1.5ns 2.0ns 5.0ns } } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock Decoder:inst9|CntTe[20] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out Decoder:inst9|CntTe[20] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 1.5ns 0.0ns } } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.000 ns" { Decoder:inst9|CntTe[20] SEGCtr:inst5|oDIG[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { Decoder:inst9|CntTe[20] SEGCtr:inst5|oDIG[0] } { 0.0ns 1.0ns } { 0.0ns 5.0ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "SEL:inst4\|Step\[5\] SW\[0\] Clock 7.000 ns register " "Info: tsu for register \"SEL:inst4\|Step\[5\]\" (data pin = \"SW\[0\]\", clock pin = \"Clock\") is 7.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SW\[0\] 1 PIN PIN_74 4 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_74; Fanout = 4; PIN Node = 'SW\[0\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { SW[0] } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { 120 752 920 136 "SW\[2..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns SEL:inst4\|Step\[5\] 2 REG LC22 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC22; Fanout = 1; REG Node = 'SEL:inst4\|Step\[5\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.000 ns" { SW[0] SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "SEL.v" "" { Text "E:/job/DelayTrigIndex/SEL.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.500 ns" { SW[0] SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { SW[0] SW[0]~out SEL:inst4|Step[5] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "SEL.v" "" { Text "E:/job/DelayTrigIndex/SEL.v" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clock 1 CLK PIN_83 65 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 65; CLK Node = 'Clock'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "" { Clock } "NODE_NAME" } "" } } { "Counter4x5.bdf" "" { Schematic "E:/job/DelayTrigIndex/Counter4x5.bdf" { { -304 -192 -24 -288 "Clock" "" } { -120 552 1088 -104 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns SEL:inst4\|Step\[5\] 2 REG LC22 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC22; Fanout = 1; REG Node = 'SEL:inst4\|Step\[5\]'" {  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "0.000 ns" { Clock SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "SEL.v" "" { Text "E:/job/DelayTrigIndex/SEL.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out SEL:inst4|Step[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}  } { { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "6.500 ns" { SW[0] SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { SW[0] SW[0]~out SEL:inst4|Step[5] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" "" { Report "E:/job/DelayTrigIndex/db/Counter4x5_cmp.qrpt" Compiler "Counter4x5" "UNKNOWN" "V1" "E:/job/DelayTrigIndex/db/Counter4x5.quartus_db" { Floorplan "E:/job/DelayTrigIndex/" "" "1.500 ns" { Clock SEL:inst4|Step[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { Clock Clock~out SEL:inst4|Step[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}