counter4x5.hier_info

完成的是RS422信号的计数功能

|Counter4x5
CameraTrig <= inst2.DB_MAX_OUTPUT_PORT_TYPE
Clock => DA2.CLK
Clock => DA1.CLK
Clock => DA4.CLK
Clock => DA3.CLK
Clock => JA0.CLK
Clock => Decoder:inst9.DClock
Clock => D2X1.CLK
Clock => D2X0.CLK
Clock => DB2.CLK
Clock => DB1.CLK
Clock => DB0.CLK
Clock => DB3.CLK
Clock => JB0.CLK
Clock => DI3.CLK
Clock => JI2.CLK
Clock => CLOCK:inst7.iCLK
APoseIn => DA4.DATAIN
BPoseIn => DB0.DATAIN
IndexIn => DI3.DATAIN
IndexIn => inst1.IN1
IndexIn => inst.IN0
SW[0] => SEL:inst4.SW[0]
SW[1] => SEL:inst4.SW[1]
SW[2] => SEL:inst4.SW[2]
MCCardTrig <= inst3.DB_MAX_OUTPUT_PORT_TYPE
SEG[0] <= SEG7_LUT:inst6.oSEG[0]
SEG[1] <= SEG7_LUT:inst6.oSEG[1]
SEG[2] <= SEG7_LUT:inst6.oSEG[2]
SEG[3] <= SEG7_LUT:inst6.oSEG[3]
SEG[4] <= SEG7_LUT:inst6.oSEG[4]
SEG[5] <= SEG7_LUT:inst6.oSEG[5]
SEG[6] <= SEG7_LUT:inst6.oSEG[6]
SEL[0] <= SEGCtr:inst5.SEL[0]
SEL[1] <= SEGCtr:inst5.SEL[1]
SEL[2] <= SEGCtr:inst5.SEL[2]
SEL[3] <= SEGCtr:inst5.SEL[3]
SEL[4] <= SEGCtr:inst5.SEL[4]
SEL[5] <= SEGCtr:inst5.SEL[5]


|Counter4x5|Decoder:inst9
AChip => always0~1.IN0
AChip => AHistr~0.DATAB
DClock => CntTe[22].CLK
DClock => CntTe[21].CLK
DClock => CntTe[20].CLK
DClock => CntTe[19].CLK
DClock => CntTe[18].CLK
DClock => CntTe[17].CLK
DClock => CntTe[16].CLK
DClock => CntTe[15].CLK
DClock => CntTe[14].CLK
DClock => CntTe[13].CLK
DClock => CntTe[12].CLK
DClock => CntTe[11].CLK
DClock => CntTe[10].CLK
DClock => CntTe[9].CLK
DClock => CntTe[8].CLK
DClock => CntTe[7].CLK
DClock => CntTe[6].CLK
DClock => CntTe[5].CLK
DClock => CntTe[4].CLK
DClock => CntTe[3].CLK
DClock => CntTe[2].CLK
DClock => CntTe[1].CLK
DClock => CntTe[0].CLK
DClock => TrigTe.CLK
DClock => AHistr.CLK
DClock => ABXorTe.CLK
DClock => CntTe[23].CLK
Cnt4X => always0~0.IN0
Cnt4X => CntTe~48.OUTPUTSELECT
Cnt4X => CntTe~49.OUTPUTSELECT
Cnt4X => CntTe~50.OUTPUTSELECT
Cnt4X => CntTe~51.OUTPUTSELECT
Cnt4X => CntTe~52.OUTPUTSELECT
Cnt4X => CntTe~53.OUTPUTSELECT
Cnt4X => CntTe~54.OUTPUTSELECT
Cnt4X => CntTe~55.OUTPUTSELECT
Cnt4X => CntTe~56.OUTPUTSELECT
Cnt4X => CntTe~57.OUTPUTSELECT
Cnt4X => CntTe~58.OUTPUTSELECT
Cnt4X => CntTe~59.OUTPUTSELECT
Cnt4X => CntTe~60.OUTPUTSELECT
Cnt4X => CntTe~61.OUTPUTSELECT
Cnt4X => CntTe~62.OUTPUTSELECT
Cnt4X => CntTe~63.OUTPUTSELECT
Cnt4X => CntTe~64.OUTPUTSELECT
Cnt4X => CntTe~65.OUTPUTSELECT
Cnt4X => CntTe~66.OUTPUTSELECT
Cnt4X => CntTe~67.OUTPUTSELECT
Cnt4X => CntTe~68.OUTPUTSELECT
Cnt4X => CntTe~69.OUTPUTSELECT
Cnt4X => CntTe~70.OUTPUTSELECT
Cnt4X => CntTe~71.OUTPUTSELECT
Cnt4X => TrigTe~2.OUTPUTSELECT
Cnt4X => ABXorTe~0.DATAB
Index => always0~19.IN0
CamrTrg <= TrigTe.DB_MAX_OUTPUT_PORT_TYPE
Step1[0] => always0~3.IN0
Step1[0] => always0~11.IN0
Step1[1] => always0~4.IN0
Step1[1] => always0~12.IN0
Step1[2] => always0~5.IN0
Step1[2] => always0~13.IN0
Step1[3] => always0~6.IN0
Step1[3] => always0~14.IN0
Step1[4] => always0~7.IN0
Step1[4] => always0~15.IN0
Step1[5] => always0~8.IN0
Step1[5] => always0~16.IN0
Step1[6] => always0~9.IN0
Step1[6] => always0~17.IN0
Step1[7] => always0~10.IN0
Step1[7] => always0~18.IN0
Count[0] <= CntTe[0].DB_MAX_OUTPUT_PORT_TYPE
Count[1] <= CntTe[1].DB_MAX_OUTPUT_PORT_TYPE
Count[2] <= CntTe[2].DB_MAX_OUTPUT_PORT_TYPE
Count[3] <= CntTe[3].DB_MAX_OUTPUT_PORT_TYPE
Count[4] <= CntTe[4].DB_MAX_OUTPUT_PORT_TYPE
Count[5] <= CntTe[5].DB_MAX_OUTPUT_PORT_TYPE
Count[6] <= CntTe[6].DB_MAX_OUTPUT_PORT_TYPE
Count[7] <= CntTe[7].DB_MAX_OUTPUT_PORT_TYPE
Count[8] <= CntTe[8].DB_MAX_OUTPUT_PORT_TYPE
Count[9] <= CntTe[9].DB_MAX_OUTPUT_PORT_TYPE
Count[10] <= CntTe[10].DB_MAX_OUTPUT_PORT_TYPE
Count[11] <= CntTe[11].DB_MAX_OUTPUT_PORT_TYPE
Count[12] <= CntTe[12].DB_MAX_OUTPUT_PORT_TYPE
Count[13] <= CntTe[13].DB_MAX_OUTPUT_PORT_TYPE
Count[14] <= CntTe[14].DB_MAX_OUTPUT_PORT_TYPE
Count[15] <= CntTe[15].DB_MAX_OUTPUT_PORT_TYPE
Count[16] <= CntTe[16].DB_MAX_OUTPUT_PORT_TYPE
Count[17] <= CntTe[17].DB_MAX_OUTPUT_PORT_TYPE
Count[18] <= CntTe[18].DB_MAX_OUTPUT_PORT_TYPE
Count[19] <= CntTe[19].DB_MAX_OUTPUT_PORT_TYPE
Count[20] <= CntTe[20].DB_MAX_OUTPUT_PORT_TYPE
Count[21] <= CntTe[21].DB_MAX_OUTPUT_PORT_TYPE
Count[22] <= CntTe[22].DB_MAX_OUTPUT_PORT_TYPE
Count[23] <= CntTe[23].DB_MAX_OUTPUT_PORT_TYPE


|Counter4x5|SEL:inst4
iCLK => Step[6]~reg0.CLK
iCLK => Step[5]~reg0.CLK
iCLK => Step[4]~reg0.CLK
iCLK => Step[3]~reg0.CLK
iCLK => Step[2]~reg0.CLK
iCLK => Step[1]~reg0.CLK
iCLK => Step[0]~reg0.CLK
iCLK => Step[7]~reg0.CLK
SW[0] => Decoder~0.IN2
SW[1] => Decoder~0.IN1
SW[2] => Decoder~0.IN0
Step[0] <= Step[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Step[1] <= Step[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Step[2] <= Step[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Step[3] <= Step[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Step[4] <= Step[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Step[5] <= Step[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Step[6] <= Step[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Step[7] <= Step[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Counter4x5|CLOCK:inst7
iCLK => CNT[15].CLK
iCLK => CNT[14].CLK
iCLK => CNT[13].CLK
iCLK => CNT[12].CLK
iCLK => CNT[11].CLK
iCLK => CNT[10].CLK
iCLK => CNT[9].CLK
iCLK => CNT[8].CLK
iCLK => CNT[7].CLK
iCLK => CNT[6].CLK
iCLK => CNT[5].CLK
iCLK => CNT[4].CLK
iCLK => CNT[3].CLK
iCLK => CNT[2].CLK
iCLK => CNT[1].CLK
iCLK => CNT[0].CLK
iCLK => CLK2.CLK
iCLK => oCLK1.DATAIN
oCLK1 <= iCLK.DB_MAX_OUTPUT_PORT_TYPE
oCLK2 <= CLK2.DB_MAX_OUTPUT_PORT_TYPE


|Counter4x5|SEG7_LUT:inst6
oSEG[0] <= oSEG[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= oSEG[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= oSEG[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= oSEG[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= oSEG[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= oSEG[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= oSEG[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|Counter4x5|SEGCtr:inst5
iCLK => cnt[6].CLK
iCLK => cnt[5].CLK
iCLK => cnt[4].CLK
iCLK => cnt[3].CLK
iCLK => cnt[2].CLK
iCLK => cnt[1].CLK
iCLK => cnt[0].CLK
iCLK => SEL[5]~reg0.CLK
iCLK => SEL[4]~reg0.CLK
iCLK => SEL[3]~reg0.CLK
iCLK => SEL[2]~reg0.CLK
iCLK => SEL[1]~reg0.CLK
iCLK => SEL[0]~reg0.CLK
iCLK => oDIG[3]~reg0.CLK
iCLK => oDIG[2]~reg0.CLK
iCLK => oDIG[1]~reg0.CLK
iCLK => oDIG[0]~reg0.CLK
iCLK => cnt[7].CLK
iRST => ~NO_FANOUT~
iDIG[0] => Select~3.IN5
iDIG[1] => Select~2.IN5
iDIG[2] => Select~1.IN5
iDIG[3] => Select~0.IN5
iDIG[4] => Select~3.IN4
iDIG[5] => Select~2.IN4
iDIG[6] => Select~1.IN4
iDIG[7] => Select~0.IN4
iDIG[8] => Select~3.IN3
iDIG[9] => Select~2.IN3
iDIG[10] => Select~1.IN3
iDIG[11] => Select~0.IN3
iDIG[12] => Select~3.IN2
iDIG[13] => Select~2.IN2
iDIG[14] => Select~1.IN2
iDIG[15] => Select~0.IN2
iDIG[16] => Select~3.IN1
iDIG[17] => Select~2.IN1
iDIG[18] => Select~1.IN1
iDIG[19] => Select~0.IN1
iDIG[20] => Select~3.IN0
iDIG[21] => Select~2.IN0
iDIG[22] => Select~1.IN0
iDIG[23] => Select~0.IN0
oDIG[0] <= oDIG[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDIG[1] <= oDIG[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDIG[2] <= oDIG[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oDIG[3] <= oDIG[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SEL[0] <= SEL[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SEL[1] <= SEL[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SEL[2] <= SEL[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SEL[3] <= SEL[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SEL[4] <= SEL[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SEL[5] <= SEL[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE