sanjiao_rom.fit.qmsg

在quartus软件下用VHDL语言实现DDS

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.319 ns memory memory " "Info: Estimated most critical path is memory to memory delay of 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_2ns:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X33_Y14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_2ns:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/sanjiao_rom_cmp.qrpt" "" { Report "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/sanjiao_rom_cmp.qrpt" Compiler "sanjiao_rom" "UNKNOWN" "V1" "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/sanjiao_rom.quartus_db" { Floorplan "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/" "" "" { altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_2ns.tdf" "" { Text "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/altsyncram_2ns.tdf" 41 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns altsyncram:altsyncram_component\|altsyncram_2ns:auto_generated\|q_a\[0\] 2 MEM M4K_X33_Y14 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_2ns:auto_generated\|q_a\[0\]'" {  } { { "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/sanjiao_rom_cmp.qrpt" "" { Report "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/sanjiao_rom_cmp.qrpt" Compiler "sanjiao_rom" "UNKNOWN" "V1" "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/sanjiao_rom.quartus_db" { Floorplan "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/" "" "4.319 ns" { altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[0] } "NODE_NAME" } "" } } { "db/altsyncram_2ns.tdf" "" { Text "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/altsyncram_2ns.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/sanjiao_rom_cmp.qrpt" "" { Report "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/sanjiao_rom_cmp.qrpt" Compiler "sanjiao_rom" "UNKNOWN" "V1" "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/sanjiao_rom.quartus_db" { Floorplan "C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/" "" "4.319 ns" { altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 01 20:55:13 2008 " "Info: Processing ended: Tue Apr 01 20:55:13 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}