📄 sanjiao_rom.fit.talkback.xml
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<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>address[4]</name>
<pin__>208</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>26</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>2</cell_number>
<combinational_fan_out>10</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>address[5]</name>
<pin__>207</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>28</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>10</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>address[6]</name>
<pin__>201</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>32</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>10</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>address[7]</name>
<pin__>203</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>30</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>10</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>address[8]</name>
<pin__>200</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>32</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>10</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>address[9]</name>
<pin__>206</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>28</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>10</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>clock</name>
<pin__>29</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>14</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>10</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>yes</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
</input_pins>
<output_pins>
<row>
<name>q[0]</name>
<pin__>100</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>32</x_coordinate>
<y_coordinate>0</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[1]</name>
<pin__>217</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>14</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[2]</name>
<pin__>158</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>19</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[3]</name>
<pin__>197</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>42</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>0</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[4]</name>
<pin__>219</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>14</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[5]</name>
<pin__>218</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>14</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[6]</name>
<pin__>99</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>32</x_coordinate>
<y_coordinate>0</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[7]</name>
<pin__>156</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>53</x_coordinate>
<y_coordinate>16</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[8]</name>
<pin__>216</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>16</x_coordinate>
<y_coordinate>27</y_coordinate>
<cell_number>2</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
<row>
<name>q[9]</name>
<pin__>88</pin__>
<i_o_bank>4</i_o_bank>
<x_coordinate>18</x_coordinate>
<y_coordinate>0</y_coordinate>
<cell_number>1</cell_number>
<output_register>no</output_register>
<output_enable_register>no</output_enable_register>
<power_up_high>no</power_up_high>
<slow_slew_rate>no</slow_slew_rate>
<pci_i_o_enabled>no</pci_i_o_enabled>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>LVTTL</i_o_standard>
<current_strength>24mA</current_strength>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
<load>Unspecified</load>
</row>
</output_pins>
<compilation_summary>
<flow_status>Successful - Tue Apr 01 20:55:13 2008</flow_status>
<quartus_ii_version>5.0 Build 148 04/26/2005 SJ Full Version</quartus_ii_version>
<revision_name>sanjiao_rom</revision_name>
<top_level_entity_name>sanjiao_rom</top_level_entity_name>
<family>Cyclone</family>
<device>EP1C12Q240C8</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>0 / 12,060 ( 0 % )</total_logic_elements>
<total_pins>23 / 173 ( 13 % )</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<total_memory_bits>40,960 / 239,616 ( 17 % )</total_memory_bits>
<total_plls>0 / 2 ( 0 % )</total_plls>
</compilation_summary>
<compile_id>EBB49DBF</compile_id>
<files>
<top>C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/sanjiao_rom.vhd</top>
<extensions>
<ext ext_name="vhd">1</ext>
<ext ext_name="tdf">2</ext>
<ext ext_name="inc">10</ext>
<ext ext_name="lst">1</ext>
<ext ext_name="mif">1</ext>
</extensions>
<sub_files>
<sub_file>C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/sanjiao_rom.vhd</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/stratix_ram_block.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/lpm_mux.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/lpm_decode.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/aglobal50.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/altsyncram.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/a_rdenreg.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/altrom.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/altram.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/altdpram.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/altqpram.inc</sub_file>
<sub_file>c:/altera/quartus50/libraries/megafunctions/cbx.lst</sub_file>
<sub_file>C:/Documents and Settings/camb/桌面/rom/sanjiao_rom/db/altsyncram_2ns.tdf</sub_file>
<sub_file>./sanjiao_rom/sanjiao_biao/sanjiao.mif</sub_file>
</sub_files>
</files>
<architecture>
<family>Cyclone</family>
<auto_device>OFF</auto_device>
<device>EP1C12Q240C8</device>
</architecture>
<pkg_io>
<pin_std count="25">LVTTL</pin_std>
</pkg_io>
<research>
<le_sclr>0</le_sclr>
<le_aclr>0</le_aclr>
<le_aload>0</le_aload>
<le_sload>0</le_sload>
<le_inverta>0</le_inverta>
<le_carry_in>0</le_carry_in>
<le_ce>0</le_ce>
<le_clk>0</le_clk>
<le_ce_sload>0</le_ce_sload>
<pin_sclr>0</pin_sclr>
<pin_aclr>0</pin_aclr>
<pin_ce_in>0</pin_ce_in>
<pin_ce_out>0</pin_ce_out>
</research>
</talkback>
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