sine_rom.tan.rpt

在quartus软件下用VHDL语言实现DDS

; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                                                                         ;
+-------+----------------------------------+------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                                                                                           ; To                                                                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+------------------------------------------------------------------------------------------------+----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg0  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg1  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg2  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg3  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg4  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg5  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg6  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg7  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg8  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg9  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg10 ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a9~porta_address_reg11 ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg0  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg1  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg2  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg3  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg4  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg5  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg6  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg7  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg8  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg9  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg10 ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a8~porta_address_reg11 ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg0  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg1  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg2  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg3  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg4  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg5  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg6  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg7  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg8  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg9  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg10 ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a7~porta_address_reg11 ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns ) ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a6~porta_address_reg0  ; altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[6] ; clock      ; clock    ; None                        ; None                      ; 4.319 ns                ;