sine_rom.map.eqn

在quartus软件下用VHDL语言实现DDS

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C1_q_a[0] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[0]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[0]_PORT_A_address_reg = DFFE(C1_q_a[0]_PORT_A_address, C1_q_a[0]_clock_0, , , );
C1_q_a[0]_clock_0 = clock;
C1_q_a[0]_PORT_A_data_out = MEMORY(, , C1_q_a[0]_PORT_A_address_reg, , , , , , C1_q_a[0]_clock_0, , , , , );
C1_q_a[0]_PORT_A_data_out_reg = DFFE(C1_q_a[0]_PORT_A_data_out, C1_q_a[0]_clock_0, , , );
C1_q_a[0] = C1_q_a[0]_PORT_A_data_out_reg[0];


--C1_q_a[1] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[1]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[1]_PORT_A_address_reg = DFFE(C1_q_a[1]_PORT_A_address, C1_q_a[1]_clock_0, , , );
C1_q_a[1]_clock_0 = clock;
C1_q_a[1]_PORT_A_data_out = MEMORY(, , C1_q_a[1]_PORT_A_address_reg, , , , , , C1_q_a[1]_clock_0, , , , , );
C1_q_a[1]_PORT_A_data_out_reg = DFFE(C1_q_a[1]_PORT_A_data_out, C1_q_a[1]_clock_0, , , );
C1_q_a[1] = C1_q_a[1]_PORT_A_data_out_reg[0];


--C1_q_a[2] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[2]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[2]_PORT_A_address_reg = DFFE(C1_q_a[2]_PORT_A_address, C1_q_a[2]_clock_0, , , );
C1_q_a[2]_clock_0 = clock;
C1_q_a[2]_PORT_A_data_out = MEMORY(, , C1_q_a[2]_PORT_A_address_reg, , , , , , C1_q_a[2]_clock_0, , , , , );
C1_q_a[2]_PORT_A_data_out_reg = DFFE(C1_q_a[2]_PORT_A_data_out, C1_q_a[2]_clock_0, , , );
C1_q_a[2] = C1_q_a[2]_PORT_A_data_out_reg[0];


--C1_q_a[3] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[3]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[3]_PORT_A_address_reg = DFFE(C1_q_a[3]_PORT_A_address, C1_q_a[3]_clock_0, , , );
C1_q_a[3]_clock_0 = clock;
C1_q_a[3]_PORT_A_data_out = MEMORY(, , C1_q_a[3]_PORT_A_address_reg, , , , , , C1_q_a[3]_clock_0, , , , , );
C1_q_a[3]_PORT_A_data_out_reg = DFFE(C1_q_a[3]_PORT_A_data_out, C1_q_a[3]_clock_0, , , );
C1_q_a[3] = C1_q_a[3]_PORT_A_data_out_reg[0];


--C1_q_a[4] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[4]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[4]_PORT_A_address_reg = DFFE(C1_q_a[4]_PORT_A_address, C1_q_a[4]_clock_0, , , );
C1_q_a[4]_clock_0 = clock;
C1_q_a[4]_PORT_A_data_out = MEMORY(, , C1_q_a[4]_PORT_A_address_reg, , , , , , C1_q_a[4]_clock_0, , , , , );
C1_q_a[4]_PORT_A_data_out_reg = DFFE(C1_q_a[4]_PORT_A_data_out, C1_q_a[4]_clock_0, , , );
C1_q_a[4] = C1_q_a[4]_PORT_A_data_out_reg[0];


--C1_q_a[5] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[5]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[5]_PORT_A_address_reg = DFFE(C1_q_a[5]_PORT_A_address, C1_q_a[5]_clock_0, , , );
C1_q_a[5]_clock_0 = clock;
C1_q_a[5]_PORT_A_data_out = MEMORY(, , C1_q_a[5]_PORT_A_address_reg, , , , , , C1_q_a[5]_clock_0, , , , , );
C1_q_a[5]_PORT_A_data_out_reg = DFFE(C1_q_a[5]_PORT_A_data_out, C1_q_a[5]_clock_0, , , );
C1_q_a[5] = C1_q_a[5]_PORT_A_data_out_reg[0];


--C1_q_a[6] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[6]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[6]_PORT_A_address_reg = DFFE(C1_q_a[6]_PORT_A_address, C1_q_a[6]_clock_0, , , );
C1_q_a[6]_clock_0 = clock;
C1_q_a[6]_PORT_A_data_out = MEMORY(, , C1_q_a[6]_PORT_A_address_reg, , , , , , C1_q_a[6]_clock_0, , , , , );
C1_q_a[6]_PORT_A_data_out_reg = DFFE(C1_q_a[6]_PORT_A_data_out, C1_q_a[6]_clock_0, , , );
C1_q_a[6] = C1_q_a[6]_PORT_A_data_out_reg[0];


--C1_q_a[7] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[7]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[7]_PORT_A_address_reg = DFFE(C1_q_a[7]_PORT_A_address, C1_q_a[7]_clock_0, , , );
C1_q_a[7]_clock_0 = clock;
C1_q_a[7]_PORT_A_data_out = MEMORY(, , C1_q_a[7]_PORT_A_address_reg, , , , , , C1_q_a[7]_clock_0, , , , , );
C1_q_a[7]_PORT_A_data_out_reg = DFFE(C1_q_a[7]_PORT_A_data_out, C1_q_a[7]_clock_0, , , );
C1_q_a[7] = C1_q_a[7]_PORT_A_data_out_reg[0];


--C1_q_a[8] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[8]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[8]_PORT_A_address_reg = DFFE(C1_q_a[8]_PORT_A_address, C1_q_a[8]_clock_0, , , );
C1_q_a[8]_clock_0 = clock;
C1_q_a[8]_PORT_A_data_out = MEMORY(, , C1_q_a[8]_PORT_A_address_reg, , , , , , C1_q_a[8]_clock_0, , , , , );
C1_q_a[8]_PORT_A_data_out_reg = DFFE(C1_q_a[8]_PORT_A_data_out, C1_q_a[8]_clock_0, , , );
C1_q_a[8] = C1_q_a[8]_PORT_A_data_out_reg[0];


--C1_q_a[9] is altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
C1_q_a[9]_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
C1_q_a[9]_PORT_A_address_reg = DFFE(C1_q_a[9]_PORT_A_address, C1_q_a[9]_clock_0, , , );
C1_q_a[9]_clock_0 = clock;
C1_q_a[9]_PORT_A_data_out = MEMORY(, , C1_q_a[9]_PORT_A_address_reg, , , , , , C1_q_a[9]_clock_0, , , , , );
C1_q_a[9]_PORT_A_data_out_reg = DFFE(C1_q_a[9]_PORT_A_data_out, C1_q_a[9]_clock_0, , , );
C1_q_a[9] = C1_q_a[9]_PORT_A_data_out_reg[0];


--clock is clock
--operation mode is input

clock = INPUT();


--address[0] is address[0]
--operation mode is input

address[0] = INPUT();


--address[1] is address[1]
--operation mode is input

address[1] = INPUT();


--address[2] is address[2]
--operation mode is input

address[2] = INPUT();


--address[3] is address[3]
--operation mode is input

address[3] = INPUT();


--address[4] is address[4]
--operation mode is input

address[4] = INPUT();


--address[5] is address[5]
--operation mode is input

address[5] = INPUT();


--address[6] is address[6]
--operation mode is input

address[6] = INPUT();


--address[7] is address[7]
--operation mode is input

address[7] = INPUT();


--address[8] is address[8]
--operation mode is input

address[8] = INPUT();


--address[9] is address[9]
--operation mode is input

address[9] = INPUT();


--address[10] is address[10]
--operation mode is input

address[10] = INPUT();


--address[11] is address[11]
--operation mode is input

address[11] = INPUT();


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(C1_q_a[0]);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(C1_q_a[1]);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(C1_q_a[2]);


--q[3] is q[3]
--operation mode is output

q[3] = OUTPUT(C1_q_a[3]);


--q[4] is q[4]
--operation mode is output

q[4] = OUTPUT(C1_q_a[4]);


--q[5] is q[5]
--operation mode is output

q[5] = OUTPUT(C1_q_a[5]);


--q[6] is q[6]
--operation mode is output

q[6] = OUTPUT(C1_q_a[6]);


--q[7] is q[7]
--operation mode is output

q[7] = OUTPUT(C1_q_a[7]);


--q[8] is q[8]
--operation mode is output

q[8] = OUTPUT(C1_q_a[8]);


--q[9] is q[9]
--operation mode is output

q[9] = OUTPUT(C1_q_a[9]);