dds.hif

在quartus软件下用VHDL语言实现DDS

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1624
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
fpq
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fpq.vhd
1207182511
4
# storage
db|dds.(0).cnf
db|dds.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
n
10
PARAMETER_DEC
DEF
}
# end
# entity
fp
# case_insensitive
# source_file
fp.bdf
1207182800
23
# storage
db|dds.(1).cnf
db|dds.(1).cnf
# hierarchies {
fp:inst
}
# end
# entity
fpq
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fpq.vhd
1207182511
4
# storage
db|dds.(2).cnf
db|dds.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
n
48
PARAMETER_UNKNOWN
USR
}
# hierarchies {
fp:inst|fpq:inst
}
# end
# entity
fpq
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fpq.vhd
1207182511
4
# storage
db|dds.(3).cnf
db|dds.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
n
1000
PARAMETER_UNKNOWN
USR
}
# hierarchies {
fp:inst|fpq:inst1
fp:inst|fpq:inst2
}
# end
# entity
fpq
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fpq.vhd
1207182511
4
# storage
db|dds.(4).cnf
db|dds.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
n
2
PARAMETER_UNKNOWN
USR
}
# hierarchies {
fp:inst|fpq:inst3
}
# end
# entity
xiaochan
# case_insensitive
# source_file
xiaochan.bdf
1207183025
23
# storage
db|dds.(5).cnf
db|dds.(5).cnf
# hierarchies {
xiaochan:inst1
}
# end
# entity
counter
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
counter.vhd
1207183192
4
# storage
db|dds.(6).cnf
db|dds.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
counter:inst2
}
# end
# entity
phase_add
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
phase_add.vhd
1207183539
4
# storage
db|dds.(8).cnf
db|dds.(8).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
phase_add:inst4
}
# end
# entity
m10
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
m10.vhd
1207183758
4
# storage
db|dds.(10).cnf
db|dds.(10).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cef:inst3|m10:inst1
cef:inst3|m10:inst2
cef:inst3|m10:inst3
cef:inst3|m10:inst4
}
# end
# entity
lock
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lock.vhd
1207183986
4
# storage
db|dds.(11).cnf
db|dds.(11).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cef:inst3|lock:inst5
}
# end
# entity
mux8_1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
mux8_1.vhd
1207184276
4
# storage
db|dds.(13).cnf
db|dds.(13).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
xianshi:inst6|mux8_1:inst
}
# end
# entity
m8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
m8.vhd
1207184364
4
# storage
db|dds.(14).cnf
db|dds.(14).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
xianshi:inst6|m8:inst1
}
# end
# entity
xianshi
# case_insensitive
# source_file
xianshi.bdf
1207184747
23
# storage
db|dds.(15).cnf
db|dds.(15).cnf
# hierarchies {
xianshi:inst6
}
# end
# entity
74138
# case_insensitive
# source_file
c:|altera|quartus50|libraries|others|maxplus2|74138.bdf
1107570360
23
# storage
db|dds.(16).cnf
db|dds.(16).cnf
# hierarchies {
xianshi:inst6|74138:inst3
}
# end
# entity
7447
# case_insensitive
# source_file
c:|altera|quartus50|libraries|others|maxplus2|7447.bdf
1107574798
23
# storage
db|dds.(17).cnf
db|dds.(17).cnf
# hierarchies {
xianshi:inst6|7447:inst2
}
# end
# entity
mux4_1
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
mux4_1.vhd
1207184871
4
# storage
db|dds.(18).cnf
db|dds.(18).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
mux4_1:inst7
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|dds.(20).cnf
db|dds.(20).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
12
PARAMETER_DEC
USR
NUMWORDS_A
4096
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./mif/sine.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_8aq
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a10
address_a11
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# end
# entity
altsyncram_8aq
# case_insensitive
# source_file
db|altsyncram_8aq.tdf
1207185463
6
# storage
db|dds.(21).cnf
db|dds.(21).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_a11
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# memory_file {
.|mif|sine.mif
1207040072
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|dds.(23).cnf
db|dds.(23).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
12
PARAMETER_DEC
USR
NUMWORDS_A
4096
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
./mif/cos.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_u6q
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a10
address_a11
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148