dds.map.qmsg

在quartus软件下用VHDL语言实现DDS

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux8_1 xianshi:inst6\|mux8_1:inst " "Info: Elaborating entity \"mux8_1\" for hierarchy \"xianshi:inst6\|mux8_1:inst\"" {  } { { "xianshi.bdf" "inst" { Schematic "D:/dds_bate4/xianshi.bdf" { { 40 264 416 264 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dis_ljone mux8_1.vhd(22) " "Warning: VHDL Process Statement warning at mux8_1.vhd(22): signal \"dis_ljone\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dis_ljten mux8_1.vhd(23) " "Warning: VHDL Process Statement warning at mux8_1.vhd(23): signal \"dis_ljten\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dis_phone mux8_1.vhd(24) " "Warning: VHDL Process Statement warning at mux8_1.vhd(24): signal \"dis_phone\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dis_phten mux8_1.vhd(25) " "Warning: VHDL Process Statement warning at mux8_1.vhd(25): signal \"dis_phten\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "f0 mux8_1.vhd(26) " "Warning: VHDL Process Statement warning at mux8_1.vhd(26): signal \"f0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "f1 mux8_1.vhd(27) " "Warning: VHDL Process Statement warning at mux8_1.vhd(27): signal \"f1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 27 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "f2 mux8_1.vhd(28) " "Warning: VHDL Process Statement warning at mux8_1.vhd(28): signal \"f2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 28 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "f3 mux8_1.vhd(29) " "Warning: VHDL Process Statement warning at mux8_1.vhd(29): signal \"f3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 29 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "mux8_1.vhd(30) " "Info: VHDL Case Statement information at mux8_1.vhd(30): OTHERS choice is never selected" {  } { { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 30 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fp fp:inst " "Info: Elaborating entity \"fp\" for hierarchy \"fp:inst\"" {  } { { "dds.bdf" "inst" { Schematic "D:/dds_bate4/dds.bdf" { { -32 216 328 96 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fpq fp:inst\|fpq:inst " "Info: Elaborating entity \"fpq\" for hierarchy \"fp:inst\|fpq:inst\"" {  } { { "fp.bdf" "inst" { Schematic "D:/dds_bate4/fp.bdf" { { 120 232 328 216 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fpq fp:inst\|fpq:inst1 " "Info: Elaborating entity \"fpq\" for hierarchy \"fp:inst\|fpq:inst1\"" {  } { { "fp.bdf" "inst1" { Schematic "D:/dds_bate4/fp.bdf" { { 216 232 328 312 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fpq fp:inst\|fpq:inst3 " "Info: Elaborating entity \"fpq\" for hierarchy \"fp:inst\|fpq:inst3\"" {  } { { "fp.bdf" "inst3" { Schematic "D:/dds_bate4/fp.bdf" { { 216 512 608 312 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst2 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst2\"" {  } { { "dds.bdf" "inst2" { Schematic "D:/dds_bate4/dds.bdf" { { 200 312 464 360 "inst2" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp_lj counter.vhd(30) " "Warning: VHDL Process Statement warning at counter.vhd(30): signal \"temp_lj\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp_lj counter.vhd(31) " "Warning: VHDL Process Statement warning at counter.vhd(31): signal \"temp_lj\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp_lj counter.vhd(32) " "Warning: VHDL Process Statement warning at counter.vhd(32): signal \"temp_lj\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp_lj counter.vhd(34) " "Warning: VHDL Process Statement warning at counter.vhd(34): signal \"temp_lj\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp_ph counter.vhd(51) " "Warning: VHDL Process Statement warning at counter.vhd(51): signal \"temp_ph\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 51 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp_ph counter.vhd(52) " "Warning: VHDL Process Statement warning at counter.vhd(52): signal \"temp_ph\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 52 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp_ph counter.vhd(54) " "Warning: VHDL Process Statement warning at counter.vhd(54): signal \"temp_ph\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 54 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp_pht counter.vhd(57) " "Warning: VHDL Process Statement warning at counter.vhd(57): signal \"temp_pht\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 57 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "xiaochan xiaochan:inst1 " "Info: Elaborating entity \"xiaochan\" for hierarchy \"xiaochan:inst1\"" {  } { { "dds.bdf" "inst1" { Schematic "D:/dds_bate4/dds.bdf" { { 200 160 288 392 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cef cef:inst3 " "Info: Elaborating entity \"cef\" for hierarchy \"cef:inst3\"" {  } { { "dds.bdf" "inst3" { Schematic "D:/dds_bate4/dds.bdf" { { 488 304 456 616 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lock cef:inst3\|lock:inst5 " "Info: Elaborating entity \"lock\" for hierarchy \"cef:inst3\|lock:inst5\"" {  } { { "cef.bdf" "inst5" { Schematic "D:/dds_bate4/cef.bdf" { { 288 536 680 416 "inst5" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "m10 cef:inst3\|m10:inst1 " "Info: Elaborating entity \"m10\" for hierarchy \"cef:inst3\|m10:inst1\"" {  } { { "cef.bdf" "inst1" { Schematic "D:/dds_bate4/cef.bdf" { { 0 336 464 96 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "leijia.vhd 2 1 " "Info: Using design file leijia.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 leijia-behavior " "Info: Found design unit 1: leijia-behavior" {  } { { "leijia.vhd" "" { Text "D:/dds_bate4/leijia.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 leijia " "Info: Found entity 1: leijia" {  } { { "leijia.vhd" "" { Text "D:/dds_bate4/leijia.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "leijia leijia:inst8 " "Info: Elaborating entity \"leijia\" for hierarchy \"leijia:inst8\"" {  } { { "dds.bdf" "inst8" { Schematic "D:/dds_bate4/dds.bdf" { { 24 520 656 120 "inst8" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp leijia.vhd(23) " "Warning: VHDL Process Statement warning at leijia.vhd(23): signal \"temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "leijia.vhd" "" { Text "D:/dds_bate4/leijia.vhd" 23 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux4_1 mux4_1:inst7 " "Info: Elaborating entity \"mux4_1\" for hierarchy \"mux4_1:inst7\"" {  } { { "dds.bdf" "inst7" { Schematic "D:/dds_bate4/dds.bdf" { { 240 1192 1352 400 "inst7" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "addr mux4_1.vhd(18) " "Warning: VHDL Process Statement warning at mux4_1.vhd(18): signal \"addr\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux4_1.vhd" "" { Text "D:/dds_bate4/mux4_1.vhd" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sine mux4_1.vhd(19) " "Warning: VHDL Process Statement warning at mux4_1.vhd(19): signal \"sine\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux4_1.vhd" "" { Text "D:/dds_bate4/mux4_1.vhd" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sanjiao mux4_1.vhd(20) " "Warning: VHDL Process Statement warning at mux4_1.vhd(20): signal \"sanjiao\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux4_1.vhd" "" { Text "D:/dds_bate4/mux4_1.vhd" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "juchi mux4_1.vhd(21) " "Warning: VHDL Process Statement warning at mux4_1.vhd(21): signal \"juchi\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux4_1.vhd" "" { Text "D:/dds_bate4/mux4_1.vhd" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "juxing mux4_1.vhd(22) " "Warning: VHDL Process Statement warning at mux4_1.vhd(22): signal \"juxing\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "mux4_1.vhd" "" { Text "D:/dds_bate4/mux4_1.vhd" 22 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "juchi_rom juchi_rom:inst28 " "Info: Elaborating entity \"juchi_rom\" for hierarchy \"juchi_rom:inst28\"" {  } { { "dds.bdf" "inst28" { Schematic "D:/dds_bate4/dds.bdf" { { 200 952 1112 280 "inst28" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}