dds.tan.qmsg

在quartus软件下用VHDL语言实现DDS

{ "Info" "ITDB_FULL_TCO_RESULT" "clk a xianshi:inst6\|m8:inst1\|m8t\[1\] 40.119 ns register " "Info: tco from clock \"clk\" to destination pin \"a\" through register \"xianshi:inst6\|m8:inst1\|m8t\[1\]\" is 40.119 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.789 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 24 192 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns fp:inst\|fpq:inst\|clkout 2 REG LC_X8_Y13_N0 674 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N0; Fanout = 674; REG Node = 'fp:inst\|fpq:inst\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.965 ns" { clk fp:inst|fpq:inst|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.586 ns) + CELL(0.935 ns) 7.955 ns fp:inst\|fpq:inst1\|clkout 3 REG LC_X7_Y12_N4 15 " "Info: 3: + IC(3.586 ns) + CELL(0.935 ns) = 7.955 ns; Loc. = LC_X7_Y12_N4; Fanout = 15; REG Node = 'fp:inst\|fpq:inst1\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.521 ns" { fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.123 ns) + CELL(0.711 ns) 12.789 ns xianshi:inst6\|m8:inst1\|m8t\[1\] 4 REG LC_X13_Y14_N2 24 " "Info: 4: + IC(4.123 ns) + CELL(0.711 ns) = 12.789 ns; Loc. = LC_X13_Y14_N2; Fanout = 24; REG Node = 'xianshi:inst6\|m8:inst1\|m8t\[1\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.834 ns" { fp:inst|fpq:inst1|clkout xianshi:inst6|m8:inst1|m8t[1] } "NODE_NAME" } "" } } { "m8.vhd" "" { Text "D:/dds_bate4/m8.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 31.67 % " "Info: Total cell delay = 4.050 ns ( 31.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.739 ns 68.33 % " "Info: Total interconnect delay = 8.739 ns ( 68.33 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "12.789 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xianshi:inst6|m8:inst1|m8t[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.789 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xianshi:inst6|m8:inst1|m8t[1] } { 0.000ns 0.000ns 1.030ns 3.586ns 4.123ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "m8.vhd" "" { Text "D:/dds_bate4/m8.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "27.106 ns + Longest register pin " "Info: + Longest register to pin delay is 27.106 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns xianshi:inst6\|m8:inst1\|m8t\[1\] 1 REG LC_X13_Y14_N2 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y14_N2; Fanout = 24; REG Node = 'xianshi:inst6\|m8:inst1\|m8t\[1\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { xianshi:inst6|m8:inst1|m8t[1] } "NODE_NAME" } "" } } { "m8.vhd" "" { Text "D:/dds_bate4/m8.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.145 ns) + CELL(0.292 ns) 4.437 ns xianshi:inst6\|74138:inst3\|15~102 2 COMB LC_X43_Y14_N1 2 " "Info: 2: + IC(4.145 ns) + CELL(0.292 ns) = 4.437 ns; Loc. = LC_X43_Y14_N1; Fanout = 2; COMB Node = 'xianshi:inst6\|74138:inst3\|15~102'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.437 ns" { xianshi:inst6|m8:inst1|m8t[1] xianshi:inst6|74138:inst3|15~102 } "NODE_NAME" } "" } } { "74138.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74138.bdf" { { 16 568 632 88 "15" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.523 ns) + CELL(0.114 ns) 7.074 ns xianshi:inst6\|mux8_1:inst\|res3~196 3 COMB LC_X24_Y14_N1 1 " "Info: 3: + IC(2.523 ns) + CELL(0.114 ns) = 7.074 ns; Loc. = LC_X24_Y14_N1; Fanout = 1; COMB Node = 'xianshi:inst6\|mux8_1:inst\|res3~196'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "2.637 ns" { xianshi:inst6|74138:inst3|15~102 xianshi:inst6|mux8_1:inst|res3~196 } "NODE_NAME" } "" } } { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(0.590 ns) 8.368 ns xianshi:inst6\|mux8_1:inst\|res3~197 4 COMB LC_X25_Y14_N8 6 " "Info: 4: + IC(0.704 ns) + CELL(0.590 ns) = 8.368 ns; Loc. = LC_X25_Y14_N8; Fanout = 6; COMB Node = 'xianshi:inst6\|mux8_1:inst\|res3~197'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.294 ns" { xianshi:inst6|mux8_1:inst|res3~196 xianshi:inst6|mux8_1:inst|res3~197 } "NODE_NAME" } "" } } { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.756 ns) + CELL(0.442 ns) 11.566 ns xianshi:inst6\|mux8_1:inst\|res1~152 5 COMB LC_X42_Y13_N9 1 " "Info: 5: + IC(2.756 ns) + CELL(0.442 ns) = 11.566 ns; Loc. = LC_X42_Y13_N9; Fanout = 1; COMB Node = 'xianshi:inst6\|mux8_1:inst\|res1~152'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "3.198 ns" { xianshi:inst6|mux8_1:inst|res3~197 xianshi:inst6|mux8_1:inst|res1~152 } "NODE_NAME" } "" } } { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.590 ns) 12.599 ns xianshi:inst6\|mux8_1:inst\|res1~153 6 COMB LC_X42_Y13_N8 2 " "Info: 6: + IC(0.443 ns) + CELL(0.590 ns) = 12.599 ns; Loc. = LC_X42_Y13_N8; Fanout = 2; COMB Node = 'xianshi:inst6\|mux8_1:inst\|res1~153'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.033 ns" { xianshi:inst6|mux8_1:inst|res1~152 xianshi:inst6|mux8_1:inst|res1~153 } "NODE_NAME" } "" } } { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(0.590 ns) 15.489 ns xianshi:inst6\|mux8_1:inst\|res1~154 7 COMB LC_X29_Y14_N0 7 " "Info: 7: + IC(2.300 ns) + CELL(0.590 ns) = 15.489 ns; Loc. = LC_X29_Y14_N0; Fanout = 7; COMB Node = 'xianshi:inst6\|mux8_1:inst\|res1~154'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "2.890 ns" { xianshi:inst6|mux8_1:inst|res1~153 xianshi:inst6|mux8_1:inst|res1~154 } "NODE_NAME" } "" } } { "mux8_1.vhd" "" { Text "D:/dds_bate4/mux8_1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.208 ns) + CELL(0.590 ns) 18.287 ns xianshi:inst6\|7447:inst2\|81~48 8 COMB LC_X42_Y14_N6 1 " "Info: 8: + IC(2.208 ns) + CELL(0.590 ns) = 18.287 ns; Loc. = LC_X42_Y14_N6; Fanout = 1; COMB Node = 'xianshi:inst6\|7447:inst2\|81~48'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "2.798 ns" { xianshi:inst6|mux8_1:inst|res1~154 xianshi:inst6|7447:inst2|81~48 } "NODE_NAME" } "" } } { "7447.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7447.bdf" { { 80 680 744 120 "81" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.186 ns) + CELL(0.114 ns) 20.587 ns xianshi:inst6\|7447:inst2\|81 9 COMB LC_X29_Y14_N2 1 " "Info: 9: + IC(2.186 ns) + CELL(0.114 ns) = 20.587 ns; Loc. = LC_X29_Y14_N2; Fanout = 1; COMB Node = 'xianshi:inst6\|7447:inst2\|81'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "2.300 ns" { xianshi:inst6|7447:inst2|81~48 xianshi:inst6|7447:inst2|81 } "NODE_NAME" } "" } } { "7447.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7447.bdf" { { 80 680 744 120 "81" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.395 ns) + CELL(2.124 ns) 27.106 ns a 10 PIN PIN_169 0 " "Info: 10: + IC(4.395 ns) + CELL(2.124 ns) = 27.106 ns; Loc. = PIN_169; Fanout = 0; PIN Node = 'a'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "6.519 ns" { xianshi:inst6|7447:inst2|81 a } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { 448 720 896 464 "a" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.446 ns 20.09 % " "Info: Total cell delay = 5.446 ns ( 20.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "21.660 ns 79.91 % " "Info: Total interconnect delay = 21.660 ns ( 79.91 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "27.106 ns" { xianshi:inst6|m8:inst1|m8t[1] xianshi:inst6|74138:inst3|15~102 xianshi:inst6|mux8_1:inst|res3~196 xianshi:inst6|mux8_1:inst|res3~197 xianshi:inst6|mux8_1:inst|res1~152 xianshi:inst6|mux8_1:inst|res1~153 xianshi:inst6|mux8_1:inst|res1~154 xianshi:inst6|7447:inst2|81~48 xianshi:inst6|7447:inst2|81 a } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "27.106 ns" { xianshi:inst6|m8:inst1|m8t[1] xianshi:inst6|74138:inst3|15~102 xianshi:inst6|mux8_1:inst|res3~196 xianshi:inst6|mux8_1:inst|res3~197 xianshi:inst6|mux8_1:inst|res1~152 xianshi:inst6|mux8_1:inst|res1~153 xianshi:inst6|mux8_1:inst|res1~154 xianshi:inst6|7447:inst2|81~48 xianshi:inst6|7447:inst2|81 a } { 0.000ns 4.145ns 2.523ns 0.704ns 2.756ns 0.443ns 2.300ns 2.208ns 2.186ns 4.395ns } { 0.000ns 0.292ns 0.114ns 0.590ns 0.442ns 0.590ns 0.590ns 0.590ns 0.114ns 2.124ns } } }  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "12.789 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xianshi:inst6|m8:inst1|m8t[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.789 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xianshi:inst6|m8:inst1|m8t[1] } { 0.000ns 0.000ns 1.030ns 3.586ns 4.123ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "27.106 ns" { xianshi:inst6|m8:inst1|m8t[1] xianshi:inst6|74138:inst3|15~102 xianshi:inst6|mux8_1:inst|res3~196 xianshi:inst6|mux8_1:inst|res3~197 xianshi:inst6|mux8_1:inst|res1~152 xianshi:inst6|mux8_1:inst|res1~153 xianshi:inst6|mux8_1:inst|res1~154 xianshi:inst6|7447:inst2|81~48 xianshi:inst6|7447:inst2|81 a } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "27.106 ns" { xianshi:inst6|m8:inst1|m8t[1] xianshi:inst6|74138:inst3|15~102 xianshi:inst6|mux8_1:inst|res3~196 xianshi:inst6|mux8_1:inst|res3~197 xianshi:inst6|mux8_1:inst|res1~152 xianshi:inst6|mux8_1:inst|res1~153 xianshi:inst6|mux8_1:inst|res1~154 xianshi:inst6|7447:inst2|81~48 xianshi:inst6|7447:inst2|81 a } { 0.000ns 4.145ns 2.523ns 0.704ns 2.756ns 0.443ns 2.300ns 2.208ns 2.186ns 4.395ns } { 0.000ns 0.292ns 0.114ns 0.590ns 0.442ns 0.590ns 0.590ns 0.590ns 0.114ns 2.124ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "addr1 DA1\[6\] 18.705 ns Longest " "Info: Longest tpd from source pin \"addr1\" to destination pin \"DA1\[6\]\" is 18.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns addr1 1 PIN PIN_141 15 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_141; Fanout = 15; PIN Node = 'addr1'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { addr1 } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { 304 -32 136 320 "addr1" "" } { 336 1120 1192 352 "addr1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(8.129 ns) + CELL(0.442 ns) 10.040 ns mux4_1:inst7\|cout\[6\]~140 2 COMB LC_X21_Y12_N1 1 " "Info: 2: + IC(8.129 ns) + CELL(0.442 ns) = 10.040 ns; Loc. = LC_X21_Y12_N1; Fanout = 1; COMB Node = 'mux4_1:inst7\|cout\[6\]~140'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "8.571 ns" { addr1 mux4_1:inst7|cout[6]~140 } "NODE_NAME" } "" } } { "mux4_1.vhd" "" { Text "D:/dds_bate4/mux4_1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.183 ns) + CELL(0.442 ns) 11.665 ns mux4_1:inst7\|cout\[6\]~141 3 COMB LC_X21_Y9_N4 1 " "Info: 3: + IC(1.183 ns) + CELL(0.442 ns) = 11.665 ns; Loc. = LC_X21_Y9_N4; Fanout = 1; COMB Node = 'mux4_1:inst7\|cout\[6\]~141'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.625 ns" { mux4_1:inst7|cout[6]~140 mux4_1:inst7|cout[6]~141 } "NODE_NAME" } "" } } { "mux4_1.vhd" "" { Text "D:/dds_bate4/mux4_1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.916 ns) + CELL(2.124 ns) 18.705 ns DA1\[6\] 4 PIN PIN_16 0 " "Info: 4: + IC(4.916 ns) + CELL(2.124 ns) = 18.705 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'DA1\[6\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "7.040 ns" { mux4_1:inst7|cout[6]~141 DA1[6] } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { 264 1368 1544 280 "DA1\[9..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.477 ns 23.93 % " "Info: Total cell delay = 4.477 ns ( 23.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.228 ns 76.07 % " "Info: Total interconnect delay = 14.228 ns ( 76.07 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "18.705 ns" { addr1 mux4_1:inst7|cout[6]~140 mux4_1:inst7|cout[6]~141 DA1[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "18.705 ns" { addr1 addr1~out0 mux4_1:inst7|cout[6]~140 mux4_1:inst7|cout[6]~141 DA1[6] } { 0.000ns 0.000ns 8.129ns 1.183ns 4.916ns } { 0.000ns 1.469ns 0.442ns 0.442ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "xiaochan:inst1\|inst reset clk 2.741 ns register " "Info: th for register \"xiaochan:inst1\|inst\" (data pin = \"reset\", clock pin = \"clk\") is 2.741 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.755 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 24 192 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns fp:inst\|fpq:inst\|clkout 2 REG LC_X8_Y13_N0 674 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N0; Fanout = 674; REG Node = 'fp:inst\|fpq:inst\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.965 ns" { clk fp:inst|fpq:inst|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.586 ns) + CELL(0.935 ns) 7.955 ns fp:inst\|fpq:inst1\|clkout 3 REG LC_X7_Y12_N4 15 " "Info: 3: + IC(3.586 ns) + CELL(0.935 ns) = 7.955 ns; Loc. = LC_X7_Y12_N4; Fanout = 15; REG Node = 'fp:inst\|fpq:inst1\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.521 ns" { fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.089 ns) + CELL(0.711 ns) 12.755 ns xiaochan:inst1\|inst 4 REG LC_X29_Y14_N8 12 " "Info: 4: + IC(4.089 ns) + CELL(0.711 ns) = 12.755 ns; Loc. = LC_X29_Y14_N8; Fanout = 12; REG Node = 'xiaochan:inst1\|inst'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.800 ns" { fp:inst|fpq:inst1|clkout xiaochan:inst1|inst } "NODE_NAME" } "" } } { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 0 280 344 80 "inst" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 31.75 % " "Info: Total cell delay = 4.050 ns ( 31.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.705 ns 68.25 % " "Info: Total interconnect delay = 8.705 ns ( 68.25 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "12.755 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.755 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst } { 0.000ns 0.000ns 1.030ns 3.586ns 4.089ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 0 280 344 80 "inst" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.029 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_121 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; PIN Node = 'reset'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { reset } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { 224 -32 136 240 "reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(8.445 ns) + CELL(0.115 ns) 10.029 ns xiaochan:inst1\|inst 2 REG LC_X29_Y14_N8 12 " "Info: 2: + IC(8.445 ns) + CELL(0.115 ns) = 10.029 ns; Loc. = LC_X29_Y14_N8; Fanout = 12; REG Node = 'xiaochan:inst1\|inst'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "8.560 ns" { reset xiaochan:inst1|inst } "NODE_NAME" } "" } } { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 0 280 344 80 "inst" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns 15.79 % " "Info: Total cell delay = 1.584 ns ( 15.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.445 ns 84.21 % " "Info: Total interconnect delay = 8.445 ns ( 84.21 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "10.029 ns" { reset xiaochan:inst1|inst } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.029 ns" { reset reset~out0 xiaochan:inst1|inst } { 0.000ns 0.000ns 8.445ns } { 0.000ns 1.469ns 0.115ns } } }  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "12.755 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.755 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst } { 0.000ns 0.000ns 1.030ns 3.586ns 4.089ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "10.029 ns" { reset xiaochan:inst1|inst } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.029 ns" { reset reset~out0 xiaochan:inst1|inst } { 0.000ns 0.000ns 8.445ns } { 0.000ns 1.469ns 0.115ns } } }  } 0}