📄 dds.tan.qmsg

📁 在quartus软件下用VHDL语言实现DDS
💻 QMSG
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{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "cef:inst3\|m10:inst1\|temp\[0\] cef:inst3\|lock:inst5\|out0\[0\] clk 2.892 ns " "Info: Found hold time violation between source  pin or register \"cef:inst3\|m10:inst1\|temp\[0\]\" and destination pin or register \"cef:inst3\|lock:inst5\|out0\[0\]\" for clock \"clk\" (Hold time is 2.892 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.799 ns + Largest " "Info: + Largest clock skew is 4.799 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 19.194 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 19.194 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 24 192 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns fp:inst\|fpq:inst\|clkout 2 REG LC_X8_Y13_N0 674 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N0; Fanout = 674; REG Node = 'fp:inst\|fpq:inst\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.965 ns" { clk fp:inst|fpq:inst|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.586 ns) + CELL(0.935 ns) 7.955 ns fp:inst\|fpq:inst1\|clkout 3 REG LC_X7_Y12_N4 15 " "Info: 3: + IC(3.586 ns) + CELL(0.935 ns) = 7.955 ns; Loc. = LC_X7_Y12_N4; Fanout = 15; REG Node = 'fp:inst\|fpq:inst1\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.521 ns" { fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.123 ns) + CELL(0.935 ns) 13.013 ns fp:inst\|fpq:inst2\|clkout 4 REG LC_X11_Y13_N5 1 " "Info: 4: + IC(4.123 ns) + CELL(0.935 ns) = 13.013 ns; Loc. = LC_X11_Y13_N5; Fanout = 1; REG Node = 'fp:inst\|fpq:inst2\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "5.058 ns" { fp:inst|fpq:inst1|clkout fp:inst|fpq:inst2|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.569 ns) + CELL(0.935 ns) 14.517 ns fp:inst\|fpq:inst3\|clkout 5 REG LC_X11_Y13_N4 36 " "Info: 5: + IC(0.569 ns) + CELL(0.935 ns) = 14.517 ns; Loc. = LC_X11_Y13_N4; Fanout = 36; REG Node = 'fp:inst\|fpq:inst3\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.504 ns" { fp:inst|fpq:inst2|clkout fp:inst|fpq:inst3|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.966 ns) + CELL(0.711 ns) 19.194 ns cef:inst3\|lock:inst5\|out0\[0\] 6 REG LC_X41_Y15_N2 1 " "Info: 6: + IC(3.966 ns) + CELL(0.711 ns) = 19.194 ns; Loc. = LC_X41_Y15_N2; Fanout = 1; REG Node = 'cef:inst3\|lock:inst5\|out0\[0\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.677 ns" { fp:inst|fpq:inst3|clkout cef:inst3|lock:inst5|out0[0] } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "D:/dds_bate4/lock.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.920 ns 30.84 % " "Info: Total cell delay = 5.920 ns ( 30.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.274 ns 69.16 % " "Info: Total interconnect delay = 13.274 ns ( 69.16 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "19.194 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout fp:inst|fpq:inst2|clkout fp:inst|fpq:inst3|clkout cef:inst3|lock:inst5|out0[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "19.194 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout fp:inst|fpq:inst2|clkout fp:inst|fpq:inst3|clkout cef:inst3|lock:inst5|out0[0] } { 0.0ns 0.0ns 1.03ns 3.586ns 4.123ns 0.569ns 3.966ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 14.395 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 14.395 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 24 192 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns fp:inst\|fpq:inst\|clkout 2 REG LC_X8_Y13_N0 674 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N0; Fanout = 674; REG Node = 'fp:inst\|fpq:inst\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.965 ns" { clk fp:inst|fpq:inst|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.621 ns) + CELL(0.935 ns) 7.990 ns leijia:inst8\|temp\[11\] 3 REG LC_X24_Y13_N5 17 " "Info: 3: + IC(3.621 ns) + CELL(0.935 ns) = 7.990 ns; Loc. = LC_X24_Y13_N5; Fanout = 17; REG Node = 'leijia:inst8\|temp\[11\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.556 ns" { fp:inst|fpq:inst|clkout leijia:inst8|temp[11] } "NODE_NAME" } "" } } { "leijia.vhd" "" { Text "D:/dds_bate4/leijia.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.694 ns) + CELL(0.711 ns) 14.395 ns cef:inst3\|m10:inst1\|temp\[0\] 4 REG LC_X44_Y13_N0 6 " "Info: 4: + IC(5.694 ns) + CELL(0.711 ns) = 14.395 ns; Loc. = LC_X44_Y13_N0; Fanout = 6; REG Node = 'cef:inst3\|m10:inst1\|temp\[0\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "6.405 ns" { leijia:inst8|temp[11] cef:inst3|m10:inst1|temp[0] } "NODE_NAME" } "" } } { "m10.vhd" "" { Text "D:/dds_bate4/m10.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 28.13 % " "Info: Total cell delay = 4.050 ns ( 28.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.345 ns 71.87 % " "Info: Total interconnect delay = 10.345 ns ( 71.87 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "14.395 ns" { clk fp:inst|fpq:inst|clkout leijia:inst8|temp[11] cef:inst3|m10:inst1|temp[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.395 ns" { clk clk~out0 fp:inst|fpq:inst|clkout leijia:inst8|temp[11] cef:inst3|m10:inst1|temp[0] } { 0.0ns 0.0ns 1.03ns 3.621ns 5.694ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "19.194 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout fp:inst|fpq:inst2|clkout fp:inst|fpq:inst3|clkout cef:inst3|lock:inst5|out0[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "19.194 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout fp:inst|fpq:inst2|clkout fp:inst|fpq:inst3|clkout cef:inst3|lock:inst5|out0[0] } { 0.0ns 0.0ns 1.03ns 3.586ns 4.123ns 0.569ns 3.966ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "14.395 ns" { clk fp:inst|fpq:inst|clkout leijia:inst8|temp[11] cef:inst3|m10:inst1|temp[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.395 ns" { clk clk~out0 fp:inst|fpq:inst|clkout leijia:inst8|temp[11] cef:inst3|m10:inst1|temp[0] } { 0.0ns 0.0ns 1.03ns 3.621ns 5.694ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "m10.vhd" "" { Text "D:/dds_bate4/m10.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.698 ns - Shortest register register " "Info: - Shortest register to register delay is 1.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cef:inst3\|m10:inst1\|temp\[0\] 1 REG LC_X44_Y13_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y13_N0; Fanout = 6; REG Node = 'cef:inst3\|m10:inst1\|temp\[0\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { cef:inst3|m10:inst1|temp[0] } "NODE_NAME" } "" } } { "m10.vhd" "" { Text "D:/dds_bate4/m10.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.583 ns) + CELL(0.115 ns) 1.698 ns cef:inst3\|lock:inst5\|out0\[0\] 2 REG LC_X41_Y15_N2 1 " "Info: 2: + IC(1.583 ns) + CELL(0.115 ns) = 1.698 ns; Loc. = LC_X41_Y15_N2; Fanout = 1; REG Node = 'cef:inst3\|lock:inst5\|out0\[0\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.698 ns" { cef:inst3|m10:inst1|temp[0] cef:inst3|lock:inst5|out0[0] } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "D:/dds_bate4/lock.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 6.77 % " "Info: Total cell delay = 0.115 ns ( 6.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.583 ns 93.23 % " "Info: Total interconnect delay = 1.583 ns ( 93.23 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.698 ns" { cef:inst3|m10:inst1|temp[0] cef:inst3|lock:inst5|out0[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.698 ns" { cef:inst3|m10:inst1|temp[0] cef:inst3|lock:inst5|out0[0] } { 0.0ns 1.583ns } { 0.0ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "lock.vhd" "" { Text "D:/dds_bate4/lock.vhd" 8 -1 0 } }  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "19.194 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout fp:inst|fpq:inst2|clkout fp:inst|fpq:inst3|clkout cef:inst3|lock:inst5|out0[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "19.194 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout fp:inst|fpq:inst2|clkout fp:inst|fpq:inst3|clkout cef:inst3|lock:inst5|out0[0] } { 0.0ns 0.0ns 1.03ns 3.586ns 4.123ns 0.569ns 3.966ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "14.395 ns" { clk fp:inst|fpq:inst|clkout leijia:inst8|temp[11] cef:inst3|m10:inst1|temp[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.395 ns" { clk clk~out0 fp:inst|fpq:inst|clkout leijia:inst8|temp[11] cef:inst3|m10:inst1|temp[0] } { 0.0ns 0.0ns 1.03ns 3.621ns 5.694ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.698 ns" { cef:inst3|m10:inst1|temp[0] cef:inst3|lock:inst5|out0[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.698 ns" { cef:inst3|m10:inst1|temp[0] cef:inst3|lock:inst5|out0[0] } { 0.0ns 1.583ns } { 0.0ns 0.115ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "xiaochan:inst1\|inst8 phone clk -1.254 ns register " "Info: tsu for register \"xiaochan:inst1\|inst8\" (data pin = \"phone\", clock pin = \"clk\") is -1.254 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.498 ns + Longest pin register " "Info: + Longest pin to register delay is 11.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns phone 1 PIN PIN_123 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_123; Fanout = 1; PIN Node = 'phone'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { phone } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { 256 -32 136 272 "phone" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(9.720 ns) + CELL(0.309 ns) 11.498 ns xiaochan:inst1\|inst8 2 REG LC_X9_Y13_N2 8 " "Info: 2: + IC(9.720 ns) + CELL(0.309 ns) = 11.498 ns; Loc. = LC_X9_Y13_N2; Fanout = 8; REG Node = 'xiaochan:inst1\|inst8'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "10.029 ns" { phone xiaochan:inst1|inst8 } "NODE_NAME" } "" } } { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 160 280 344 240 "inst8" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 15.46 % " "Info: Total cell delay = 1.778 ns ( 15.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.720 ns 84.54 % " "Info: Total interconnect delay = 9.720 ns ( 84.54 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "11.498 ns" { phone xiaochan:inst1|inst8 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.498 ns" { phone phone~out0 xiaochan:inst1|inst8 } { 0.000ns 0.000ns 9.720ns } { 0.000ns 1.469ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 160 280 344 240 "inst8" "" } } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.789 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 12.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 24 192 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns fp:inst\|fpq:inst\|clkout 2 REG LC_X8_Y13_N0 674 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N0; Fanout = 674; REG Node = 'fp:inst\|fpq:inst\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.965 ns" { clk fp:inst|fpq:inst|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.586 ns) + CELL(0.935 ns) 7.955 ns fp:inst\|fpq:inst1\|clkout 3 REG LC_X7_Y12_N4 15 " "Info: 3: + IC(3.586 ns) + CELL(0.935 ns) = 7.955 ns; Loc. = LC_X7_Y12_N4; Fanout = 15; REG Node = 'fp:inst\|fpq:inst1\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.521 ns" { fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.123 ns) + CELL(0.711 ns) 12.789 ns xiaochan:inst1\|inst8 4 REG LC_X9_Y13_N2 8 " "Info: 4: + IC(4.123 ns) + CELL(0.711 ns) = 12.789 ns; Loc. = LC_X9_Y13_N2; Fanout = 8; REG Node = 'xiaochan:inst1\|inst8'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.834 ns" { fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 } "NODE_NAME" } "" } } { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 160 280 344 240 "inst8" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 31.67 % " "Info: Total cell delay = 4.050 ns ( 31.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.739 ns 68.33 % " "Info: Total interconnect delay = 8.739 ns ( 68.33 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "12.789 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.789 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 } { 0.000ns 0.000ns 1.030ns 3.586ns 4.123ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "11.498 ns" { phone xiaochan:inst1|inst8 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.498 ns" { phone phone~out0 xiaochan:inst1|inst8 } { 0.000ns 0.000ns 9.720ns } { 0.000ns 1.469ns 0.309ns } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "12.789 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.789 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 } { 0.000ns 0.000ns 1.030ns 3.586ns 4.123ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0}
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