dds.tan.qmsg

在quartus软件下用VHDL语言实现DDS

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 24 192 8 "clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cef:inst3\|m10:inst3\|co " "Info: Detected ripple clock \"cef:inst3\|m10:inst3\|co\" as buffer" {  } { { "m10.vhd" "" { Text "D:/dds_bate4/m10.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cef:inst3\|m10:inst3\|co" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cef:inst3\|m10:inst2\|co " "Info: Detected ripple clock \"cef:inst3\|m10:inst2\|co\" as buffer" {  } { { "m10.vhd" "" { Text "D:/dds_bate4/m10.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cef:inst3\|m10:inst2\|co" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "cef:inst3\|m10:inst1\|co " "Info: Detected ripple clock \"cef:inst3\|m10:inst1\|co\" as buffer" {  } { { "m10.vhd" "" { Text "D:/dds_bate4/m10.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cef:inst3\|m10:inst1\|co" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "leijia:inst8\|temp\[11\] " "Info: Detected ripple clock \"leijia:inst8\|temp\[11\]\" as buffer" {  } { { "leijia.vhd" "" { Text "D:/dds_bate4/leijia.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "leijia:inst8\|temp\[11\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fp:inst\|fpq:inst2\|clkout " "Info: Detected ripple clock \"fp:inst\|fpq:inst2\|clkout\" as buffer" {  } { { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fp:inst\|fpq:inst2\|clkout" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fp:inst\|fpq:inst3\|clkout " "Info: Detected ripple clock \"fp:inst\|fpq:inst3\|clkout\" as buffer" {  } { { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fp:inst\|fpq:inst3\|clkout" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fp:inst\|fpq:inst\|clkout " "Info: Detected ripple clock \"fp:inst\|fpq:inst\|clkout\" as buffer" {  } { { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fp:inst\|fpq:inst\|clkout" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fp:inst\|fpq:inst1\|clkout " "Info: Detected ripple clock \"fp:inst\|fpq:inst1\|clkout\" as buffer" {  } { { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fp:inst\|fpq:inst1\|clkout" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "xiaochan:inst1\|inst4 " "Info: Detected ripple clock \"xiaochan:inst1\|inst4\" as buffer" {  } { { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 80 344 408 160 "inst4" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "xiaochan:inst1\|inst4" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "xiaochan:inst1\|inst8 " "Info: Detected ripple clock \"xiaochan:inst1\|inst8\" as buffer" {  } { { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 160 280 344 240 "inst8" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "xiaochan:inst1\|inst8" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter:inst2\|temp_pht\[8\] memory sine_rom:inst31\|altsyncram:altsyncram_component\|altsyncram_0qr:auto_generated\|ram_block1a5~porta_address_reg9 58.41 MHz 17.121 ns Internal " "Info: Clock \"clk\" has Internal fmax of 58.41 MHz between source register \"counter:inst2\|temp_pht\[8\]\" and destination memory \"sine_rom:inst31\|altsyncram:altsyncram_component\|altsyncram_0qr:auto_generated\|ram_block1a5~porta_address_reg9\" (period= 17.121 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.803 ns + Longest register memory " "Info: + Longest register to memory delay is 6.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst2\|temp_pht\[8\] 1 REG LC_X25_Y13_N7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y13_N7; Fanout = 7; REG Node = 'counter:inst2\|temp_pht\[8\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { counter:inst2|temp_pht[8] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.575 ns) 1.138 ns phase_add:inst4\|add~183COUT1_202 2 COMB LC_X25_Y13_N1 2 " "Info: 2: + IC(0.563 ns) + CELL(0.575 ns) = 1.138 ns; Loc. = LC_X25_Y13_N1; Fanout = 2; COMB Node = 'phase_add:inst4\|add~183COUT1_202'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.138 ns" { counter:inst2|temp_pht[8] phase_add:inst4|add~183COUT1_202 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.746 ns phase_add:inst4\|add~186 3 COMB LC_X25_Y13_N2 40 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 1.746 ns; Loc. = LC_X25_Y13_N2; Fanout = 40; COMB Node = 'phase_add:inst4\|add~186'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "0.608 ns" { phase_add:inst4|add~183COUT1_202 phase_add:inst4|add~186 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.674 ns) + CELL(0.383 ns) 6.803 ns sine_rom:inst31\|altsyncram:altsyncram_component\|altsyncram_0qr:auto_generated\|ram_block1a5~porta_address_reg9 4 MEM M4K_X33_Y7 1 " "Info: 4: + IC(4.674 ns) + CELL(0.383 ns) = 6.803 ns; Loc. = M4K_X33_Y7; Fanout = 1; MEM Node = 'sine_rom:inst31\|altsyncram:altsyncram_component\|altsyncram_0qr:auto_generated\|ram_block1a5~porta_address_reg9'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "5.057 ns" { phase_add:inst4|add~186 sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } "NODE_NAME" } "" } } { "db/altsyncram_0qr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_0qr.tdf" 136 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.566 ns 23.02 % " "Info: Total cell delay = 1.566 ns ( 23.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.237 ns 76.98 % " "Info: Total interconnect delay = 5.237 ns ( 76.98 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "6.803 ns" { counter:inst2|temp_pht[8] phase_add:inst4|add~183COUT1_202 phase_add:inst4|add~186 sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.803 ns" { counter:inst2|temp_pht[8] phase_add:inst4|add~183COUT1_202 phase_add:inst4|add~186 sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } { 0.000ns 0.563ns 0.000ns 4.674ns } { 0.000ns 0.575ns 0.608ns 0.383ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-10.001 ns - Smallest " "Info: - Smallest clock skew is -10.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.681 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 7.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 24 192 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns fp:inst\|fpq:inst\|clkout 2 REG LC_X8_Y13_N0 674 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N0; Fanout = 674; REG Node = 'fp:inst\|fpq:inst\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.965 ns" { clk fp:inst|fpq:inst|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.525 ns) + CELL(0.722 ns) 7.681 ns sine_rom:inst31\|altsyncram:altsyncram_component\|altsyncram_0qr:auto_generated\|ram_block1a5~porta_address_reg9 3 MEM M4K_X33_Y7 1 " "Info: 3: + IC(3.525 ns) + CELL(0.722 ns) = 7.681 ns; Loc. = M4K_X33_Y7; Fanout = 1; MEM Node = 'sine_rom:inst31\|altsyncram:altsyncram_component\|altsyncram_0qr:auto_generated\|ram_block1a5~porta_address_reg9'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.247 ns" { fp:inst|fpq:inst|clkout sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } "NODE_NAME" } "" } } { "db/altsyncram_0qr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_0qr.tdf" 136 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns 40.70 % " "Info: Total cell delay = 3.126 ns ( 40.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.555 ns 59.30 % " "Info: Total interconnect delay = 4.555 ns ( 59.30 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "7.681 ns" { clk fp:inst|fpq:inst|clkout sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.681 ns" { clk clk~out0 fp:inst|fpq:inst|clkout sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } { 0.000ns 0.000ns 1.030ns 3.525ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 17.682 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 17.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'clk'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { clk } "NODE_NAME" } "" } } { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 24 192 8 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns fp:inst\|fpq:inst\|clkout 2 REG LC_X8_Y13_N0 674 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N0; Fanout = 674; REG Node = 'fp:inst\|fpq:inst\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.965 ns" { clk fp:inst|fpq:inst|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.586 ns) + CELL(0.935 ns) 7.955 ns fp:inst\|fpq:inst1\|clkout 3 REG LC_X7_Y12_N4 15 " "Info: 3: + IC(3.586 ns) + CELL(0.935 ns) = 7.955 ns; Loc. = LC_X7_Y12_N4; Fanout = 15; REG Node = 'fp:inst\|fpq:inst1\|clkout'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.521 ns" { fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout } "NODE_NAME" } "" } } { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.123 ns) + CELL(0.935 ns) 13.013 ns xiaochan:inst1\|inst8 4 REG LC_X9_Y13_N2 8 " "Info: 4: + IC(4.123 ns) + CELL(0.935 ns) = 13.013 ns; Loc. = LC_X9_Y13_N2; Fanout = 8; REG Node = 'xiaochan:inst1\|inst8'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "5.058 ns" { fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 } "NODE_NAME" } "" } } { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 160 280 344 240 "inst8" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.958 ns) + CELL(0.711 ns) 17.682 ns counter:inst2\|temp_pht\[8\] 5 REG LC_X25_Y13_N7 7 " "Info: 5: + IC(3.958 ns) + CELL(0.711 ns) = 17.682 ns; Loc. = LC_X25_Y13_N7; Fanout = 7; REG Node = 'counter:inst2\|temp_pht\[8\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.669 ns" { xiaochan:inst1|inst8 counter:inst2|temp_pht[8] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.985 ns 28.19 % " "Info: Total cell delay = 4.985 ns ( 28.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.697 ns 71.81 % " "Info: Total interconnect delay = 12.697 ns ( 71.81 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "17.682 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 counter:inst2|temp_pht[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.682 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 counter:inst2|temp_pht[8] } { 0.000ns 0.000ns 1.030ns 3.586ns 4.123ns 3.958ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "7.681 ns" { clk fp:inst|fpq:inst|clkout sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.681 ns" { clk clk~out0 fp:inst|fpq:inst|clkout sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } { 0.000ns 0.000ns 1.030ns 3.525ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "17.682 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 counter:inst2|temp_pht[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.682 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 counter:inst2|temp_pht[8] } { 0.000ns 0.000ns 1.030ns 3.586ns 4.123ns 3.958ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_0qr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_0qr.tdf" 136 2 0 } }  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "6.803 ns" { counter:inst2|temp_pht[8] phase_add:inst4|add~183COUT1_202 phase_add:inst4|add~186 sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.803 ns" { counter:inst2|temp_pht[8] phase_add:inst4|add~183COUT1_202 phase_add:inst4|add~186 sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } { 0.000ns 0.563ns 0.000ns 4.674ns } { 0.000ns 0.575ns 0.608ns 0.383ns } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "7.681 ns" { clk fp:inst|fpq:inst|clkout sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.681 ns" { clk clk~out0 fp:inst|fpq:inst|clkout sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 } { 0.000ns 0.000ns 1.030ns 3.525ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "17.682 ns" { clk fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 counter:inst2|temp_pht[8] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "17.682 ns" { clk clk~out0 fp:inst|fpq:inst|clkout fp:inst|fpq:inst1|clkout xiaochan:inst1|inst8 counter:inst2|temp_pht[8] } { 0.000ns 0.000ns 1.030ns 3.586ns 4.123ns 3.958ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0}