dds.fit.qmsg

在quartus软件下用VHDL语言实现DDS

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.926 ns register memory " "Info: Estimated most critical path is register to memory delay of 4.926 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst2\|temp_pht\[10\] 1 REG LAB_X23_Y13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X23_Y13; Fanout = 5; REG Node = 'counter:inst2\|temp_pht\[10\]'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { counter:inst2|temp_pht[10] } "NODE_NAME" } "" } } { "counter.vhd" "" { Text "D:/dds_bate4/counter.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.249 ns) + CELL(0.432 ns) 1.681 ns phase_add:inst4\|add~193COUT1_203 2 COMB LAB_X25_Y13 1 " "Info: 2: + IC(1.249 ns) + CELL(0.432 ns) = 1.681 ns; Loc. = LAB_X25_Y13; Fanout = 1; COMB Node = 'phase_add:inst4\|add~193COUT1_203'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "1.681 ns" { counter:inst2|temp_pht[10] phase_add:inst4|add~193COUT1_203 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.289 ns phase_add:inst4\|add~196 3 COMB LAB_X25_Y13 40 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 2.289 ns; Loc. = LAB_X25_Y13; Fanout = 40; COMB Node = 'phase_add:inst4\|add~196'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "0.608 ns" { phase_add:inst4|add~193COUT1_203 phase_add:inst4|add~196 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.254 ns) + CELL(0.383 ns) 4.926 ns sanjiao_rom:inst27\|altsyncram:altsyncram_component\|altsyncram_2ns:auto_generated\|ram_block1a1~porta_address_reg11 4 MEM M4K_X33_Y2 1 " "Info: 4: + IC(2.254 ns) + CELL(0.383 ns) = 4.926 ns; Loc. = M4K_X33_Y2; Fanout = 1; MEM Node = 'sanjiao_rom:inst27\|altsyncram:altsyncram_component\|altsyncram_2ns:auto_generated\|ram_block1a1~porta_address_reg11'" {  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "2.637 ns" { phase_add:inst4|add~196 sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a1~porta_address_reg11 } "NODE_NAME" } "" } } { "db/altsyncram_2ns.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2ns.tdf" 60 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.423 ns 28.89 % " "Info: Total cell delay = 1.423 ns ( 28.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.503 ns 71.11 % " "Info: Total interconnect delay = 3.503 ns ( 71.11 % )" {  } {  } 0}  } { { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "4.926 ns" { counter:inst2|temp_pht[10] phase_add:inst4|add~193COUT1_203 phase_add:inst4|add~196 sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a1~porta_address_reg11 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 3 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 3%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: The following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DA1_mode GND " "Info: Pin DA1_mode has GND driving its datain port" {  } { { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -56 960 1136 -40 "DA1_mode" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DA1_mode" } } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { DA1_mode } "NODE_NAME" } "" } } { "D:/dds_bate4/dds.fld" "" { Floorplan "D:/dds_bate4/dds.fld" "" "" { DA1_mode } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DA2_mode GND " "Info: Pin DA2_mode has GND driving its datain port" {  } { { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -72 960 1136 -56 "DA2_mode" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "DA2_mode" } } } } { "D:/dds_bate4/db/dds_cmp.qrpt" "" { Report "D:/dds_bate4/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/dds_bate4/db/dds.quartus_db" { Floorplan "D:/dds_bate4/" "" "" { DA2_mode } "NODE_NAME" } "" } } { "D:/dds_bate4/dds.fld" "" { Floorplan "D:/dds_bate4/dds.fld" "" "" { DA2_mode } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 03 15:45:56 2008 " "Info: Processing ended: Thu Apr 03 15:45:56 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}