dds.fit.qmsg

在quartus软件下用VHDL语言实现DDS

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 03 15:45:47 2008 " "Info: Processing started: Thu Apr 03 15:45:47 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "dds EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"dds\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 153 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 153" {  } { { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 24 192 8 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fp:inst\|fpq:inst\|clkout Global clock " "Info: Automatically promoted some destinations of signal \"fp:inst\|fpq:inst\|clkout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DA_clk " "Info: Destination \"DA_clk\" may be non-global or may not use global clock" {  } { { "dds.bdf" "" { Schematic "D:/dds_bate4/dds.bdf" { { -8 960 1136 8 "DA_clk" "" } } } }  } 0}  } { { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fp:inst\|fpq:inst3\|clkout Global clock " "Info: Automatically promoted some destinations of signal \"fp:inst\|fpq:inst3\|clkout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fp:inst\|fpq:inst3\|clkout " "Info: Destination \"fp:inst\|fpq:inst3\|clkout\" may be non-global or may not use global clock" {  } { { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0}  } { { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fp:inst\|fpq:inst1\|clkout Global clock " "Info: Automatically promoted signal \"fp:inst\|fpq:inst1\|clkout\" to use Global clock" {  } { { "fpq.vhd" "" { Text "D:/dds_bate4/fpq.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "xiaochan:inst1\|inst8 Global clock " "Info: Automatically promoted signal \"xiaochan:inst1\|inst8\" to use Global clock" {  } { { "xiaochan.bdf" "" { Schematic "D:/dds_bate4/xiaochan.bdf" { { 160 280 344 240 "inst8" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cef:inst3\|m10:inst1\|co Global clock " "Info: Automatically promoted signal \"cef:inst3\|m10:inst1\|co\" to use Global clock" {  } { { "m10.vhd" "" { Text "D:/dds_bate4/m10.vhd" 10 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cef:inst3\|m10:inst2\|co Global clock " "Info: Automatically promoted signal \"cef:inst3\|m10:inst2\|co\" to use Global clock" {  } { { "m10.vhd" "" { Text "D:/dds_bate4/m10.vhd" 10 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "leijia:inst8\|temp\[11\] Global clock " "Info: Automatically promoted some destinations of signal \"leijia:inst8\|temp\[11\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a0 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a0\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a1 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a1\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a2 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a2\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a3 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a3\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a4 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a4\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a5 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a5\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a6 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a6\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a7 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a7\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a8 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a8\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a9 " "Info: Destination \"cos_rom:inst38\|altsyncram:altsyncram_component\|altsyncram_2gr:auto_generated\|ram_block1a9\" may be non-global or may not use global clock" {  } { { "db/altsyncram_2gr.tdf" "" { Text "D:/dds_bate4/db/altsyncram_2gr.tdf" 38 2 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "leijia.vhd" "" { Text "D:/dds_bate4/leijia.vhd" 14 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}