⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 dds.map.eqn

📁 在quartus软件下用VHDL语言实现DDS
💻 EQN
📖 第 1 页 / 共 5 页
字号:
🔍
12345 
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[7]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_clock_0 = Q1_clkout;
Y1_q_a[7]_PORT_A_data_out = MEMORY(, , Y1_q_a[7]_PORT_A_address_reg, , , , , , Y1_q_a[7]_clock_0, , , , , );
Y1_q_a[7]_PORT_A_data_out_reg = DFFE(Y1_q_a[7]_PORT_A_data_out, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7] = Y1_q_a[7]_PORT_A_data_out_reg[0];


--Z1_q_a[7] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[7]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = Q1_clkout;
Z1_q_a[7]_PORT_A_data_out = MEMORY(, , Z1_q_a[7]_PORT_A_address_reg, , , , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7] = Z1_q_a[7]_PORT_A_data_out_reg[0];


--BB1_q_a[7] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[7]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
BB1_q_a[7]_PORT_A_address_reg = DFFE(BB1_q_a[7]_PORT_A_address, BB1_q_a[7]_clock_0, , , );
BB1_q_a[7]_clock_0 = Q1_clkout;
BB1_q_a[7]_PORT_A_data_out = MEMORY(, , BB1_q_a[7]_PORT_A_address_reg, , , , , , BB1_q_a[7]_clock_0, , , , , );
BB1_q_a[7]_PORT_A_data_out_reg = DFFE(BB1_q_a[7]_PORT_A_data_out, BB1_q_a[7]_clock_0, , , );
BB1_q_a[7] = BB1_q_a[7]_PORT_A_data_out_reg[0];


--H1L51 is mux4_1:inst7|cout[7]~138
--operation mode is normal

H1L51 = addr0 & (addr1) # !addr0 & (addr1 & Z1_q_a[7] # !addr1 & (BB1_q_a[7]));


--AB1_q_a[7] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[7]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = Q1_clkout;
AB1_q_a[7]_PORT_A_data_out = MEMORY(, , AB1_q_a[7]_PORT_A_address_reg, , , , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7] = AB1_q_a[7]_PORT_A_data_out_reg[0];


--H1L61 is mux4_1:inst7|cout[7]~139
--operation mode is normal

H1L61 = addr0 & (H1L51 & (AB1_q_a[7]) # !H1L51 & Y1_q_a[7]) # !addr0 & (H1L51);


--Z1_q_a[6] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[6]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Z1_q_a[6]_PORT_A_address_reg = DFFE(Z1_q_a[6]_PORT_A_address, Z1_q_a[6]_clock_0, , , );
Z1_q_a[6]_clock_0 = Q1_clkout;
Z1_q_a[6]_PORT_A_data_out = MEMORY(, , Z1_q_a[6]_PORT_A_address_reg, , , , , , Z1_q_a[6]_clock_0, , , , , );
Z1_q_a[6]_PORT_A_data_out_reg = DFFE(Z1_q_a[6]_PORT_A_data_out, Z1_q_a[6]_clock_0, , , );
Z1_q_a[6] = Z1_q_a[6]_PORT_A_data_out_reg[0];


--Y1_q_a[6] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[6]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Y1_q_a[6]_PORT_A_address_reg = DFFE(Y1_q_a[6]_PORT_A_address, Y1_q_a[6]_clock_0, , , );
Y1_q_a[6]_clock_0 = Q1_clkout;
Y1_q_a[6]_PORT_A_data_out = MEMORY(, , Y1_q_a[6]_PORT_A_address_reg, , , , , , Y1_q_a[6]_clock_0, , , , , );
Y1_q_a[6]_PORT_A_data_out_reg = DFFE(Y1_q_a[6]_PORT_A_data_out, Y1_q_a[6]_clock_0, , , );
Y1_q_a[6] = Y1_q_a[6]_PORT_A_data_out_reg[0];


--BB1_q_a[6] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[6]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
BB1_q_a[6]_PORT_A_address_reg = DFFE(BB1_q_a[6]_PORT_A_address, BB1_q_a[6]_clock_0, , , );
BB1_q_a[6]_clock_0 = Q1_clkout;
BB1_q_a[6]_PORT_A_data_out = MEMORY(, , BB1_q_a[6]_PORT_A_address_reg, , , , , , BB1_q_a[6]_clock_0, , , , , );
BB1_q_a[6]_PORT_A_data_out_reg = DFFE(BB1_q_a[6]_PORT_A_data_out, BB1_q_a[6]_clock_0, , , );
BB1_q_a[6] = BB1_q_a[6]_PORT_A_data_out_reg[0];


--H1L31 is mux4_1:inst7|cout[6]~140
--operation mode is normal

H1L31 = addr1 & (addr0) # !addr1 & (addr0 & Y1_q_a[6] # !addr0 & (BB1_q_a[6]));


--AB1_q_a[6] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[6]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
AB1_q_a[6]_PORT_A_address_reg = DFFE(AB1_q_a[6]_PORT_A_address, AB1_q_a[6]_clock_0, , , );
AB1_q_a[6]_clock_0 = Q1_clkout;
AB1_q_a[6]_PORT_A_data_out = MEMORY(, , AB1_q_a[6]_PORT_A_address_reg, , , , , , AB1_q_a[6]_clock_0, , , , , );
AB1_q_a[6]_PORT_A_data_out_reg = DFFE(AB1_q_a[6]_PORT_A_data_out, AB1_q_a[6]_clock_0, , , );
AB1_q_a[6] = AB1_q_a[6]_PORT_A_data_out_reg[0];


--H1L41 is mux4_1:inst7|cout[6]~141
--operation mode is normal

H1L41 = addr1 & (H1L31 & (AB1_q_a[6]) # !H1L31 & Z1_q_a[6]) # !addr1 & (H1L31);


--Y1_q_a[5] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[5]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Y1_q_a[5]_PORT_A_address_reg = DFFE(Y1_q_a[5]_PORT_A_address, Y1_q_a[5]_clock_0, , , );
Y1_q_a[5]_clock_0 = Q1_clkout;
Y1_q_a[5]_PORT_A_data_out = MEMORY(, , Y1_q_a[5]_PORT_A_address_reg, , , , , , Y1_q_a[5]_clock_0, , , , , );
Y1_q_a[5]_PORT_A_data_out_reg = DFFE(Y1_q_a[5]_PORT_A_data_out, Y1_q_a[5]_clock_0, , , );
Y1_q_a[5] = Y1_q_a[5]_PORT_A_data_out_reg[0];


--Z1_q_a[5] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[5]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Z1_q_a[5]_PORT_A_address_reg = DFFE(Z1_q_a[5]_PORT_A_address, Z1_q_a[5]_clock_0, , , );
Z1_q_a[5]_clock_0 = Q1_clkout;
Z1_q_a[5]_PORT_A_data_out = MEMORY(, , Z1_q_a[5]_PORT_A_address_reg, , , , , , Z1_q_a[5]_clock_0, , , , , );
Z1_q_a[5]_PORT_A_data_out_reg = DFFE(Z1_q_a[5]_PORT_A_data_out, Z1_q_a[5]_clock_0, , , );
Z1_q_a[5] = Z1_q_a[5]_PORT_A_data_out_reg[0];


--BB1_q_a[5] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[5]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
BB1_q_a[5]_PORT_A_address_reg = DFFE(BB1_q_a[5]_PORT_A_address, BB1_q_a[5]_clock_0, , , );
BB1_q_a[5]_clock_0 = Q1_clkout;
BB1_q_a[5]_PORT_A_data_out = MEMORY(, , BB1_q_a[5]_PORT_A_address_reg, , , , , , BB1_q_a[5]_clock_0, , , , , );
BB1_q_a[5]_PORT_A_data_out_reg = DFFE(BB1_q_a[5]_PORT_A_data_out, BB1_q_a[5]_clock_0, , , );
BB1_q_a[5] = BB1_q_a[5]_PORT_A_data_out_reg[0];


--H1L11 is mux4_1:inst7|cout[5]~142
--operation mode is normal

H1L11 = addr0 & (addr1) # !addr0 & (addr1 & Z1_q_a[5] # !addr1 & (BB1_q_a[5]));


--AB1_q_a[5] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[5]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
AB1_q_a[5]_PORT_A_address_reg = DFFE(AB1_q_a[5]_PORT_A_address, AB1_q_a[5]_clock_0, , , );
AB1_q_a[5]_clock_0 = Q1_clkout;
AB1_q_a[5]_PORT_A_data_out = MEMORY(, , AB1_q_a[5]_PORT_A_address_reg, , , , , , AB1_q_a[5]_clock_0, , , , , );
AB1_q_a[5]_PORT_A_data_out_reg = DFFE(AB1_q_a[5]_PORT_A_data_out, AB1_q_a[5]_clock_0, , , );
AB1_q_a[5] = AB1_q_a[5]_PORT_A_data_out_reg[0];


--H1L21 is mux4_1:inst7|cout[5]~143
--operation mode is normal

H1L21 = addr0 & (H1L11 & (AB1_q_a[5]) # !H1L11 & Y1_q_a[5]) # !addr0 & (H1L11);


--Z1_q_a[4] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[4]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Z1_q_a[4]_PORT_A_address_reg = DFFE(Z1_q_a[4]_PORT_A_address, Z1_q_a[4]_clock_0, , , );
Z1_q_a[4]_clock_0 = Q1_clkout;
Z1_q_a[4]_PORT_A_data_out = MEMORY(, , Z1_q_a[4]_PORT_A_address_reg, , , , , , Z1_q_a[4]_clock_0, , , , , );
Z1_q_a[4]_PORT_A_data_out_reg = DFFE(Z1_q_a[4]_PORT_A_data_out, Z1_q_a[4]_clock_0, , , );
Z1_q_a[4] = Z1_q_a[4]_PORT_A_data_out_reg[0];


--Y1_q_a[4] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[4]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Y1_q_a[4]_PORT_A_address_reg = DFFE(Y1_q_a[4]_PORT_A_address, Y1_q_a[4]_clock_0, , , );
Y1_q_a[4]_clock_0 = Q1_clkout;
Y1_q_a[4]_PORT_A_data_out = MEMORY(, , Y1_q_a[4]_PORT_A_address_reg, , , , , , Y1_q_a[4]_clock_0, , , , , );
Y1_q_a[4]_PORT_A_data_out_reg = DFFE(Y1_q_a[4]_PORT_A_data_out, Y1_q_a[4]_clock_0, , , );
Y1_q_a[4] = Y1_q_a[4]_PORT_A_data_out_reg[0];


--BB1_q_a[4] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[4]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
BB1_q_a[4]_PORT_A_address_reg = DFFE(BB1_q_a[4]_PORT_A_address, BB1_q_a[4]_clock_0, , , );
BB1_q_a[4]_clock_0 = Q1_clkout;
BB1_q_a[4]_PORT_A_data_out = MEMORY(, , BB1_q_a[4]_PORT_A_address_reg, , , , , , BB1_q_a[4]_clock_0, , , , , );
BB1_q_a[4]_PORT_A_data_out_reg = DFFE(BB1_q_a[4]_PORT_A_data_out, BB1_q_a[4]_clock_0, , , );
BB1_q_a[4] = BB1_q_a[4]_PORT_A_data_out_reg[0];


--H1L9 is mux4_1:inst7|cout[4]~144
--operation mode is normal

H1L9 = addr1 & (addr0) # !addr1 & (addr0 & Y1_q_a[4] # !addr0 & (BB1_q_a[4]));


--AB1_q_a[4] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[4]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
AB1_q_a[4]_PORT_A_address_reg = DFFE(AB1_q_a[4]_PORT_A_address, AB1_q_a[4]_clock_0, , , );
AB1_q_a[4]_clock_0 = Q1_clkout;
AB1_q_a[4]_PORT_A_data_out = MEMORY(, , AB1_q_a[4]_PORT_A_address_reg, , , , , , AB1_q_a[4]_clock_0, , , , , );
AB1_q_a[4]_PORT_A_data_out_reg = DFFE(AB1_q_a[4]_PORT_A_data_out, AB1_q_a[4]_clock_0, , , );
AB1_q_a[4] = AB1_q_a[4]_PORT_A_data_out_reg[0];


--H1L01 is mux4_1:inst7|cout[4]~145
--operation mode is normal

H1L01 = addr1 & (H1L9 & (AB1_q_a[4]) # !H1L9 & Z1_q_a[4]) # !addr1 & (H1L9);


--Y1_q_a[3] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[3]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Y1_q_a[3]_PORT_A_address_reg = DFFE(Y1_q_a[3]_PORT_A_address, Y1_q_a[3]_clock_0, , , );
Y1_q_a[3]_clock_0 = Q1_clkout;
Y1_q_a[3]_PORT_A_data_out = MEMORY(, , Y1_q_a[3]_PORT_A_address_reg, , , , , , Y1_q_a[3]_clock_0, , , , , );
Y1_q_a[3]_PORT_A_data_out_reg = DFFE(Y1_q_a[3]_PORT_A_data_out, Y1_q_a[3]_clock_0, , , );
Y1_q_a[3] = Y1_q_a[3]_PORT_A_data_out_reg[0];


--Z1_q_a[3] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[3]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
Z1_q_a[3]_PORT_A_address_reg = DFFE(Z1_q_a[3]_PORT_A_address, Z1_q_a[3]_clock_0, , , );
Z1_q_a[3]_clock_0 = Q1_clkout;
Z1_q_a[3]_PORT_A_data_out = MEMORY(, , Z1_q_a[3]_PORT_A_address_reg, , , , , , Z1_q_a[3]_clock_0, , , , , );
Z1_q_a[3]_PORT_A_data_out_reg = DFFE(Z1_q_a[3]_PORT_A_data_out, Z1_q_a[3]_clock_0, , , );
Z1_q_a[3] = Z1_q_a[3]_PORT_A_data_out_reg[0];


--BB1_q_a[3] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[3]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
BB1_q_a[3]_PORT_A_address_reg = DFFE(BB1_q_a[3]_PORT_A_address, BB1_q_a[3]_clock_0, , , );
BB1_q_a[3]_clock_0 = Q1_clkout;
BB1_q_a[3]_PORT_A_data_out = MEMORY(, , BB1_q_a[3]_PORT_A_address_reg, , , , , , BB1_q_a[3]_clock_0, , , , , );
BB1_q_a[3]_PORT_A_data_out_reg = DFFE(BB1_q_a[3]_PORT_A_data_out, BB1_q_a[3]_clock_0, , , );
BB1_q_a[3] = BB1_q_a[3]_PORT_A_data_out_reg[0];


--H1L7 is mux4_1:inst7|cout[3]~146
--operation mode is normal

H1L7 = addr0 & (addr1) # !addr0 & (addr1 & Z1_q_a[3] # !addr1 & (BB1_q_a[3]));


--AB1_q_a[3] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[3]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L3, F1L5, F1L7);
AB1_q_a[3]_PORT_A_address_reg = DFFE(AB1_q_a[3]_PORT_A_address, AB1_q_a[3]_clock_0, , , );
AB1_q_a[3]_clock_0 = Q1_clkout;
AB1_q_a[3]_PORT_A_data_out = MEMORY(, , AB1_q_a[3]_PORT_A_address_reg, , , , , , AB1_q_a[3]_clock_0, , , , , );
AB1_q_a[3]_PORT_A_data_out_reg = DFFE(AB1_q_a[3]_PORT_A_data_out, AB1_q_a[3]_clock_0, , , );
AB1_q_a[3] = AB1_q_a[3]_PORT_A_data_out_reg[0];
12345

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -