dds.tan.rpt

在quartus软件下用VHDL语言实现DDS

; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; cef:inst3|m10:inst1|temp[0]   ; cef:inst3|lock:inst5|out0[0]                                                                                  ; clk        ; clk      ; 8            ;
; Total number of failed paths ;                                          ;               ;                                  ;                               ;                                                                                                               ;            ;          ; 8            ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------+---------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------+-------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                       ; To                                                                                                                ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------+-------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 58.41 MHz ( period = 17.121 ns )                    ; counter:inst2|temp_pht[8]  ; sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9     ; clk        ; clk      ; None                        ; None                      ; 6.803 ns                ;
; N/A                                     ; 58.64 MHz ( period = 17.052 ns )                    ; counter:inst2|temp_pht[10] ; sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a1~porta_address_reg11 ; clk        ; clk      ; None                        ; None                      ; 6.734 ns                ;
; N/A                                     ; 58.91 MHz ( period = 16.974 ns )                    ; counter:inst2|temp_pht[10] ; juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|ram_block1a0~porta_address_reg11   ; clk        ; clk      ; None                        ; None                      ; 6.717 ns                ;
; N/A                                     ; 59.64 MHz ( period = 16.767 ns )                    ; counter:inst2|temp_pht[8]  ; juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|ram_block1a2~porta_address_reg9   ; clk        ; clk      ; None                        ; None                      ; 6.449 ns                ;
; N/A                                     ; 59.66 MHz ( period = 16.763 ns )                    ; counter:inst2|temp_pht[8]  ; sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a0~porta_address_reg9  ; clk        ; clk      ; None                        ; None                      ; 6.445 ns                ;
; N/A                                     ; 59.68 MHz ( period = 16.757 ns )                    ; counter:inst2|temp_pht[8]  ; juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|ram_block1a2~porta_address_reg9    ; clk        ; clk      ; None                        ; None                      ; 6.439 ns                ;
; N/A                                     ; 59.99 MHz ( period = 16.669 ns )                    ; counter:inst2|temp_pht[8]  ; sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a0~porta_address_reg9     ; clk        ; clk      ; None                        ; None                      ; 6.351 ns                ;