📄 juxing_rom.map.rpt
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; -- Total 4-input functions ; 0 ;
; -- Total 3-input functions ; 0 ;
; -- Total 2-input functions ; 0 ;
; -- Total 1-input functions ; 0 ;
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 0 ;
; I/O pins ; 23 ;
; Total memory bits ; 40960 ;
; Maximum fan-out node ; clock ;
; Maximum fan-out ; 10 ;
; Total fan-out ; 140 ;
; Average fan-out ; 4.24 ;
+---------------------------------+-----------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------+
; |juxing_rom ; 0 (0) ; 0 ; 40960 ; 23 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |juxing_rom ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 40960 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |juxing_rom|altsyncram:altsyncram_component ;
; |altsyncram_ifs:auto_generated| ; 0 (0) ; 0 ; 40960 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |juxing_rom|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------+
; altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 4096 ; 10 ; -- ; -- ; 40960 ; None ;
+--------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: altsyncram:altsyncram_component ;
+------------------------------------+-------------------------------------+----------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-------------------------------------+----------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 10 ; Integer ;
; WIDTHAD_A ; 12 ; Integer ;
; NUMWORDS_A ; 4096 ; Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; ./juxing_rom/juxing_biao/juxing.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_ifs ; Untyped ;
+------------------------------------+-------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/dds_bate3/juxing_rom/juxing_rom.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Apr 02 09:39:00 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off juxing_rom -c juxing_rom
Info: Using design file juxing_rom.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: juxing_rom-SYN
Info: Found entity 1: juxing_rom
Info: Elaborating entity "juxing_rom" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ifs.tdf
Info: Found entity 1: altsyncram_ifs
Info: Elaborating entity "altsyncram_ifs" for hierarchy "altsyncram:altsyncram_component|altsyncram_ifs:auto_generated"
Warning: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File ./juxing_rom/juxing_biao/juxing.mif -- setting all initial values to 0
Info: Implemented 33 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 10 output pins
Info: Implemented 10 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Processing ended: Wed Apr 02 09:39:01 2008
Info: Elapsed time: 00:00:02
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