dds.fit.eqn

在quartus软件下用VHDL语言实现DDS

--CB1_q_a[7] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[7] at M4K_X33_Y23
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[7]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[7]_PORT_A_address_reg = DFFE(CB1_q_a[7]_PORT_A_address, CB1_q_a[7]_clock_0, , , );
CB1_q_a[7]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[7]_PORT_A_data_out = MEMORY(, , CB1_q_a[7]_PORT_A_address_reg, , , , , , CB1_q_a[7]_clock_0, , , , , );
CB1_q_a[7]_PORT_A_data_out_reg = DFFE(CB1_q_a[7]_PORT_A_data_out, CB1_q_a[7]_clock_0, , , );
CB1_q_a[7] = CB1_q_a[7]_PORT_A_data_out_reg[0];


--CB1_q_a[6] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[6] at M4K_X33_Y22
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[6]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[6]_PORT_A_address_reg = DFFE(CB1_q_a[6]_PORT_A_address, CB1_q_a[6]_clock_0, , , );
CB1_q_a[6]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[6]_PORT_A_data_out = MEMORY(, , CB1_q_a[6]_PORT_A_address_reg, , , , , , CB1_q_a[6]_clock_0, , , , , );
CB1_q_a[6]_PORT_A_data_out_reg = DFFE(CB1_q_a[6]_PORT_A_data_out, CB1_q_a[6]_clock_0, , , );
CB1_q_a[6] = CB1_q_a[6]_PORT_A_data_out_reg[0];


--CB1_q_a[5] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[5] at M4K_X19_Y22
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[5]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[5]_PORT_A_address_reg = DFFE(CB1_q_a[5]_PORT_A_address, CB1_q_a[5]_clock_0, , , );
CB1_q_a[5]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[5]_PORT_A_data_out = MEMORY(, , CB1_q_a[5]_PORT_A_address_reg, , , , , , CB1_q_a[5]_clock_0, , , , , );
CB1_q_a[5]_PORT_A_data_out_reg = DFFE(CB1_q_a[5]_PORT_A_data_out, CB1_q_a[5]_clock_0, , , );
CB1_q_a[5] = CB1_q_a[5]_PORT_A_data_out_reg[0];


--CB1_q_a[4] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[4] at M4K_X19_Y23
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[4]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[4]_PORT_A_address_reg = DFFE(CB1_q_a[4]_PORT_A_address, CB1_q_a[4]_clock_0, , , );
CB1_q_a[4]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[4]_PORT_A_data_out = MEMORY(, , CB1_q_a[4]_PORT_A_address_reg, , , , , , CB1_q_a[4]_clock_0, , , , , );
CB1_q_a[4]_PORT_A_data_out_reg = DFFE(CB1_q_a[4]_PORT_A_data_out, CB1_q_a[4]_clock_0, , , );
CB1_q_a[4] = CB1_q_a[4]_PORT_A_data_out_reg[0];


--CB1_q_a[3] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[3] at M4K_X19_Y21
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[3]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[3]_PORT_A_address_reg = DFFE(CB1_q_a[3]_PORT_A_address, CB1_q_a[3]_clock_0, , , );
CB1_q_a[3]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[3]_PORT_A_data_out = MEMORY(, , CB1_q_a[3]_PORT_A_address_reg, , , , , , CB1_q_a[3]_clock_0, , , , , );
CB1_q_a[3]_PORT_A_data_out_reg = DFFE(CB1_q_a[3]_PORT_A_data_out, CB1_q_a[3]_clock_0, , , );
CB1_q_a[3] = CB1_q_a[3]_PORT_A_data_out_reg[0];


--CB1_q_a[2] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[2] at M4K_X33_Y25
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[2]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[2]_PORT_A_address_reg = DFFE(CB1_q_a[2]_PORT_A_address, CB1_q_a[2]_clock_0, , , );
CB1_q_a[2]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[2]_PORT_A_data_out = MEMORY(, , CB1_q_a[2]_PORT_A_address_reg, , , , , , CB1_q_a[2]_clock_0, , , , , );
CB1_q_a[2]_PORT_A_data_out_reg = DFFE(CB1_q_a[2]_PORT_A_data_out, CB1_q_a[2]_clock_0, , , );
CB1_q_a[2] = CB1_q_a[2]_PORT_A_data_out_reg[0];


--CB1_q_a[1] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[1] at M4K_X19_Y26
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[1]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[1]_PORT_A_address_reg = DFFE(CB1_q_a[1]_PORT_A_address, CB1_q_a[1]_clock_0, , , );
CB1_q_a[1]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[1]_PORT_A_data_out = MEMORY(, , CB1_q_a[1]_PORT_A_address_reg, , , , , , CB1_q_a[1]_clock_0, , , , , );
CB1_q_a[1]_PORT_A_data_out_reg = DFFE(CB1_q_a[1]_PORT_A_data_out, CB1_q_a[1]_clock_0, , , );
CB1_q_a[1] = CB1_q_a[1]_PORT_A_data_out_reg[0];


--CB1_q_a[0] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[0] at M4K_X19_Y25
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[0]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[0]_PORT_A_address_reg = DFFE(CB1_q_a[0]_PORT_A_address, CB1_q_a[0]_clock_0, , , );
CB1_q_a[0]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[0]_PORT_A_data_out = MEMORY(, , CB1_q_a[0]_PORT_A_address_reg, , , , , , CB1_q_a[0]_clock_0, , , , , );
CB1_q_a[0]_PORT_A_data_out_reg = DFFE(CB1_q_a[0]_PORT_A_data_out, CB1_q_a[0]_clock_0, , , );
CB1_q_a[0] = CB1_q_a[0]_PORT_A_data_out_reg[0];


--Q3L1 is fp:inst|fpq:inst2|add~151 at LC_X12_Y13_N0
--operation mode is arithmetic

Q3L1 = !Q3_temp[0];

--Q3L2 is fp:inst|fpq:inst2|add~153 at LC_X12_Y13_N0
--operation mode is arithmetic

Q3L2_cout_0 = Q3_temp[0];
Q3L2 = CARRY(Q3L2_cout_0);

--Q3L3 is fp:inst|fpq:inst2|add~153COUT1_202 at LC_X12_Y13_N0
--operation mode is arithmetic

Q3L3_cout_1 = Q3_temp[0];
Q3L3 = CARRY(Q3L3_cout_1);


--Q2_clkout is fp:inst|fpq:inst1|clkout at LC_X7_Y12_N4
--operation mode is normal

Q2_clkout_lut_out = !Q2L13;
Q2_clkout = DFFEAS(Q2_clkout_lut_out, GLOBAL(Q1_clkout), VCC, , , , , , );


--C1_inst8 is xiaochan:inst1|inst8 at LC_X9_Y13_N2
--operation mode is normal

C1_inst8_lut_out = phone;
C1_inst8 = DFFEAS(C1_inst8_lut_out, GLOBAL(Q2_clkout), VCC, , , , , , );


--C1_inst4 is xiaochan:inst1|inst4 at LC_X25_Y14_N1
--operation mode is normal

C1_inst4_lut_out = GND;
C1_inst4 = DFFEAS(C1_inst4_lut_out, GLOBAL(Q2_clkout), VCC, , , leijia, , , VCC);


--D1L7 is counter:inst2|add~724 at LC_X29_Y14_N6
--operation mode is normal

D1L7 = D1_temp_ph[0] & (D1_temp_ph[1]);


--D1L8 is counter:inst2|add~725 at LC_X26_Y14_N2
--operation mode is normal

D1L8 = D1_temp_lj[1] & D1_temp_lj[0];


--D1L9 is counter:inst2|add~726 at LC_X24_Y14_N2
--operation mode is normal

D1L9 = D1_temp_lj[2] & (D1_temp_lj[1] & D1_temp_lj[0]);


--D1L01 is counter:inst2|add~727 at LC_X29_Y14_N9
--operation mode is normal

D1L01 = D1_temp_ph[0] & D1_temp_ph[1] & (D1_temp_ph[2]);


--R2_temp[2] is cef:inst3|m10:inst2|temp[2] at LC_X41_Y13_N2
--operation mode is normal

R2_temp[2]_lut_out = !R2_temp[2];
R2_temp[2] = DFFEAS(R2_temp[2]_lut_out, GLOBAL(R1_co), !GLOBAL(Q4_clkout), , R2L1, , , , );


--Q4_clkout is fp:inst|fpq:inst3|clkout at LC_X11_Y13_N4
--operation mode is normal

Q4_clkout_lut_out = !Q4_clkout;
Q4_clkout = DFFEAS(Q4_clkout_lut_out, Q3_clkout, VCC, , , , , , );


--R1_temp[2] is cef:inst3|m10:inst1|temp[2] at LC_X44_Y13_N9
--operation mode is normal

R1_temp[2]_lut_out = !R1_temp[2];
R1_temp[2] = DFFEAS(R1_temp[2]_lut_out, GLOBAL(J1_temp[11]), !GLOBAL(Q4_clkout), , R1L1, , , , );


--R3_temp[2] is cef:inst3|m10:inst3|temp[2] at LC_X42_Y14_N9
--operation mode is normal

R3_temp[2]_lut_out = !R3_temp[2];
R3_temp[2] = DFFEAS(R3_temp[2]_lut_out, GLOBAL(R2_co), !GLOBAL(Q4_clkout), , R3L1, , , , );


--R4_temp[2] is cef:inst3|m10:inst4|temp[2] at LC_X40_Y14_N2
--operation mode is normal

R4_temp[2]_lut_out = !R4_temp[2];
R4_temp[2] = DFFEAS(R4_temp[2]_lut_out, R3_co, !GLOBAL(Q4_clkout), , R4L1, , , , );


--R2_temp[1] is cef:inst3|m10:inst2|temp[1] at LC_X42_Y13_N6
--operation mode is normal

R2_temp[1]_lut_out = R2_temp[1] & !R2_temp[0] # !R2_temp[1] & R2_temp[0] & (R2_temp[2] # !R2_temp[3]);
R2_temp[1] = DFFEAS(R2_temp[1]_lut_out, GLOBAL(R1_co), !GLOBAL(Q4_clkout), , , , , , );


--R1_temp[1] is cef:inst3|m10:inst1|temp[1] at LC_X44_Y13_N5
--operation mode is normal

R1_temp[1]_lut_out = R1_temp[1] & (!R1_temp[0]) # !R1_temp[1] & R1_temp[0] & (R1_temp[2] # !R1_temp[3]);
R1_temp[1] = DFFEAS(R1_temp[1]_lut_out, GLOBAL(J1_temp[11]), !GLOBAL(Q4_clkout), , , , , , );


--R3_temp[1] is cef:inst3|m10:inst3|temp[1] at LC_X41_Y14_N2
--operation mode is normal

R3_temp[1]_lut_out = R3_temp[1] & (!R3_temp[0]) # !R3_temp[1] & R3_temp[0] & (R3_temp[2] # !R3_temp[3]);
R3_temp[1] = DFFEAS(R3_temp[1]_lut_out, GLOBAL(R2_co), !GLOBAL(Q4_clkout), , , , , , );


--R4_temp[1] is cef:inst3|m10:inst4|temp[1] at LC_X40_Y14_N5
--operation mode is normal

R4_temp[1]_lut_out = R4_temp[1] & (!R4_temp[0]) # !R4_temp[1] & R4_temp[0] & (R4_temp[2] # !R4_temp[3]);
R4_temp[1] = DFFEAS(R4_temp[1]_lut_out, R3_co, !GLOBAL(Q4_clkout), , , , , , );


--R2_temp[3] is cef:inst3|m10:inst2|temp[3] at LC_X42_Y13_N7
--operation mode is normal

R2_temp[3]_lut_out = R2_temp[1] & (R2_temp[3] $ (R2_temp[0] & R2_temp[2])) # !R2_temp[1] & R2_temp[3] & (R2_temp[2] # !R2_temp[0]);
R2_temp[3] = DFFEAS(R2_temp[3]_lut_out, GLOBAL(R1_co), !GLOBAL(Q4_clkout), , , , , , );


--R1_temp[3] is cef:inst3|m10:inst1|temp[3] at LC_X44_Y13_N2
--operation mode is normal

R1_temp[3]_lut_out = R1_temp[3] & (R1_temp[1] $ R1_temp[2] # !R1_temp[0]) # !R1_temp[3] & R1_temp[1] & R1_temp[2] & R1_temp[0];
R1_temp[3] = DFFEAS(R1_temp[3]_lut_out, GLOBAL(J1_temp[11]), !GLOBAL(Q4_clkout), , , , , , );


--R3_temp[3] is cef:inst3|m10:inst3|temp[3] at LC_X41_Y14_N0
--operation mode is normal

R3_temp[3]_lut_out = R3_temp[1] & (R3_temp[3] $ (R3_temp[2] & R3_temp[0])) # !R3_temp[1] & R3_temp[3] & (R3_temp[2] # !R3_temp[0]);
R3_temp[3] = DFFEAS(R3_temp[3]_lut_out, GLOBAL(R2_co), !GLOBAL(Q4_clkout), , , , , , );


--R4_temp[3] is cef:inst3|m10:inst4|temp[3] at LC_X40_Y14_N6
--operation mode is normal

R4_temp[3]_lut_out = R4_temp[3] & (R4_temp[1] $ R4_temp[2] # !R4_temp[0]) # !R4_temp[3] & R4_temp[1] & R4_temp[2] & R4_temp[0];
R4_temp[3] = DFFEAS(R4_temp[3]_lut_out, R3_co, !GLOBAL(Q4_clkout), , , , , , );


--R3_temp[0] is cef:inst3|m10:inst3|temp[0] at LC_X41_Y14_N9
--operation mode is normal

R3_temp[0]_lut_out = !R3_temp[0];
R3_temp[0] = DFFEAS(R3_temp[0]_lut_out, GLOBAL(R2_co), !GLOBAL(Q4_clkout), , , , , , );


--R2_temp[0] is cef:inst3|m10:inst2|temp[0] at LC_X42_Y13_N0
--operation mode is normal

R2_temp[0]_lut_out = !R2_temp[0];
R2_temp[0] = DFFEAS(R2_temp[0]_lut_out, GLOBAL(R1_co), !GLOBAL(Q4_clkout), , , , , , );


--R1_temp[0] is cef:inst3|m10:inst1|temp[0] at LC_X44_Y13_N0
--operation mode is normal

R1_temp[0]_lut_out = !R1_temp[0];
R1_temp[0] = DFFEAS(R1_temp[0]_lut_out, GLOBAL(J1_temp[11]), !GLOBAL(Q4_clkout), , , , , , );


--R4_temp[0] is cef:inst3|m10:inst4|temp[0] at LC_X40_Y14_N0
--operation mode is normal

R4_temp[0]_lut_out = !R4_tem