📄 dds.fit.eqn
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--operation mode is normal
H1L01 = addr1 & (H1L9 & AB1_q_a[4] # !H1L9 & (Z1_q_a[4])) # !addr1 & H1L9;
--Y1_q_a[3] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[3] at M4K_X33_Y9
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[3]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[3]_PORT_A_address_reg = DFFE(Y1_q_a[3]_PORT_A_address, Y1_q_a[3]_clock_0, , , );
Y1_q_a[3]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[3]_PORT_A_data_out = MEMORY(, , Y1_q_a[3]_PORT_A_address_reg, , , , , , Y1_q_a[3]_clock_0, , , , , );
Y1_q_a[3]_PORT_A_data_out_reg = DFFE(Y1_q_a[3]_PORT_A_data_out, Y1_q_a[3]_clock_0, , , );
Y1_q_a[3] = Y1_q_a[3]_PORT_A_data_out_reg[0];
--Z1_q_a[3] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[3] at M4K_X33_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[3]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[3]_PORT_A_address_reg = DFFE(Z1_q_a[3]_PORT_A_address, Z1_q_a[3]_clock_0, , , );
Z1_q_a[3]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[3]_PORT_A_data_out = MEMORY(, , Z1_q_a[3]_PORT_A_address_reg, , , , , , Z1_q_a[3]_clock_0, , , , , );
Z1_q_a[3]_PORT_A_data_out_reg = DFFE(Z1_q_a[3]_PORT_A_data_out, Z1_q_a[3]_clock_0, , , );
Z1_q_a[3] = Z1_q_a[3]_PORT_A_data_out_reg[0];
--BB1_q_a[3] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[3] at M4K_X33_Y21
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[3]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[3]_PORT_A_address_reg = DFFE(BB1_q_a[3]_PORT_A_address, BB1_q_a[3]_clock_0, , , );
BB1_q_a[3]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[3]_PORT_A_data_out = MEMORY(, , BB1_q_a[3]_PORT_A_address_reg, , , , , , BB1_q_a[3]_clock_0, , , , , );
BB1_q_a[3]_PORT_A_data_out_reg = DFFE(BB1_q_a[3]_PORT_A_data_out, BB1_q_a[3]_clock_0, , , );
BB1_q_a[3] = BB1_q_a[3]_PORT_A_data_out_reg[0];
--H1L7 is mux4_1:inst7|cout[3]~146 at LC_X35_Y12_N9
--operation mode is normal
H1L7 = addr1 & (Z1_q_a[3] # addr0) # !addr1 & (BB1_q_a[3] & !addr0);
--AB1_q_a[3] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[3] at M4K_X33_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[3]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[3]_PORT_A_address_reg = DFFE(AB1_q_a[3]_PORT_A_address, AB1_q_a[3]_clock_0, , , );
AB1_q_a[3]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[3]_PORT_A_data_out = MEMORY(, , AB1_q_a[3]_PORT_A_address_reg, , , , , , AB1_q_a[3]_clock_0, , , , , );
AB1_q_a[3]_PORT_A_data_out_reg = DFFE(AB1_q_a[3]_PORT_A_data_out, AB1_q_a[3]_clock_0, , , );
AB1_q_a[3] = AB1_q_a[3]_PORT_A_data_out_reg[0];
--H1L8 is mux4_1:inst7|cout[3]~147 at LC_X35_Y12_N3
--operation mode is normal
H1L8 = H1L7 & (AB1_q_a[3] # !addr0) # !H1L7 & addr0 & Y1_q_a[3];
--Z1_q_a[2] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[2] at M4K_X33_Y5
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[2]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[2]_PORT_A_address_reg = DFFE(Z1_q_a[2]_PORT_A_address, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[2]_PORT_A_data_out = MEMORY(, , Z1_q_a[2]_PORT_A_address_reg, , , , , , Z1_q_a[2]_clock_0, , , , , );
Z1_q_a[2]_PORT_A_data_out_reg = DFFE(Z1_q_a[2]_PORT_A_data_out, Z1_q_a[2]_clock_0, , , );
Z1_q_a[2] = Z1_q_a[2]_PORT_A_data_out_reg[0];
--Y1_q_a[2] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[2] at M4K_X33_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[2]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[2]_PORT_A_address_reg = DFFE(Y1_q_a[2]_PORT_A_address, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[2]_PORT_A_data_out = MEMORY(, , Y1_q_a[2]_PORT_A_address_reg, , , , , , Y1_q_a[2]_clock_0, , , , , );
Y1_q_a[2]_PORT_A_data_out_reg = DFFE(Y1_q_a[2]_PORT_A_data_out, Y1_q_a[2]_clock_0, , , );
Y1_q_a[2] = Y1_q_a[2]_PORT_A_data_out_reg[0];
--BB1_q_a[2] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[2] at M4K_X33_Y18
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[2]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[2]_PORT_A_address_reg = DFFE(BB1_q_a[2]_PORT_A_address, BB1_q_a[2]_clock_0, , , );
BB1_q_a[2]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[2]_PORT_A_data_out = MEMORY(, , BB1_q_a[2]_PORT_A_address_reg, , , , , , BB1_q_a[2]_clock_0, , , , , );
BB1_q_a[2]_PORT_A_data_out_reg = DFFE(BB1_q_a[2]_PORT_A_data_out, BB1_q_a[2]_clock_0, , , );
BB1_q_a[2] = BB1_q_a[2]_PORT_A_data_out_reg[0];
--H1L5 is mux4_1:inst7|cout[2]~148 at LC_X35_Y12_N6
--operation mode is normal
H1L5 = addr1 & addr0 # !addr1 & (addr0 & Y1_q_a[2] # !addr0 & (BB1_q_a[2]));
--AB1_q_a[2] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[2] at M4K_X33_Y6
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[2]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[2]_PORT_A_address_reg = DFFE(AB1_q_a[2]_PORT_A_address, AB1_q_a[2]_clock_0, , , );
AB1_q_a[2]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[2]_PORT_A_data_out = MEMORY(, , AB1_q_a[2]_PORT_A_address_reg, , , , , , AB1_q_a[2]_clock_0, , , , , );
AB1_q_a[2]_PORT_A_data_out_reg = DFFE(AB1_q_a[2]_PORT_A_data_out, AB1_q_a[2]_clock_0, , , );
AB1_q_a[2] = AB1_q_a[2]_PORT_A_data_out_reg[0];
--H1L6 is mux4_1:inst7|cout[2]~149 at LC_X35_Y12_N7
--operation mode is normal
H1L6 = addr1 & (H1L5 & (AB1_q_a[2]) # !H1L5 & Z1_q_a[2]) # !addr1 & (H1L5);
--Y1_q_a[1] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[1] at M4K_X33_Y2
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[1]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[1]_PORT_A_address_reg = DFFE(Y1_q_a[1]_PORT_A_address, Y1_q_a[1]_clock_0, , , );
Y1_q_a[1]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[1]_PORT_A_data_out = MEMORY(, , Y1_q_a[1]_PORT_A_address_reg, , , , , , Y1_q_a[1]_clock_0, , , , , );
Y1_q_a[1]_PORT_A_data_out_reg = DFFE(Y1_q_a[1]_PORT_A_data_out, Y1_q_a[1]_clock_0, , , );
Y1_q_a[1] = Y1_q_a[1]_PORT_A_data_out_reg[0];
--Z1_q_a[1] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[1] at M4K_X19_Y18
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[1]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[1]_PORT_A_address_reg = DFFE(Z1_q_a[1]_PORT_A_address, Z1_q_a[1]_clock_0, , , );
Z1_q_a[1]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[1]_PORT_A_data_out = MEMORY(, , Z1_q_a[1]_PORT_A_address_reg, , , , , , Z1_q_a[1]_clock_0, , , , , );
Z1_q_a[1]_PORT_A_data_out_reg = DFFE(Z1_q_a[1]_PORT_A_data_out, Z1_q_a[1]_clock_0, , , );
Z1_q_a[1] = Z1_q_a[1]_PORT_A_data_out_reg[0];
--BB1_q_a[1] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[1] at M4K_X19_Y6
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[1]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[1]_PORT_A_address_reg = DFFE(BB1_q_a[1]_PORT_A_address, BB1_q_a[1]_clock_0, , , );
BB1_q_a[1]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[1]_PORT_A_data_out = MEMORY(, , BB1_q_a[1]_PORT_A_address_reg, , , , , , BB1_q_a[1]_clock_0, , , , , );
BB1_q_a[1]_PORT_A_data_out_reg = DFFE(BB1_q_a[1]_PORT_A_data_out, BB1_q_a[1]_clock_0, , , );
BB1_q_a[1] = BB1_q_a[1]_PORT_A_data_out_reg[0];
--H1L3 is mux4_1:inst7|cout[1]~150 at LC_X21_Y12_N5
--operation mode is normal
H1L3 = addr1 & (addr0 # Z1_q_a[1]) # !addr1 & BB1_q_a[1] & !addr0;
--AB1_q_a[1] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[1] at M4K_X19_Y5
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[1]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[1]_PORT_A_address_reg = DFFE(AB1_q_a[1]_PORT_A_address, AB1_q_a[1]_clock_0, , , );
AB1_q_a[1]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[1]_PORT_A_data_out = MEMORY(, , AB1_q_a[1]_PORT_A_address_reg, , , , , , AB1_q_a[1]_clock_0, , , , , );
AB1_q_a[1]_PORT_A_data_out_reg = DFFE(AB1_q_a[1]_PORT_A_data_out, AB1_q_a[1]_clock_0, , , );
AB1_q_a[1] = AB1_q_a[1]_PORT_A_data_out_reg[0];
--H1L4 is mux4_1:inst7|cout[1]~151 at LC_X21_Y12_N6
--operation mode is normal
H1L4 = addr0 & (H1L3 & (AB1_q_a[1]) # !H1L3 & Y1_q_a[1]) # !addr0 & H1L3;
--Z1_q_a[0] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[0] at M4K_X19_Y1
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[0]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[0]_PORT_A_address_reg = DFFE(Z1_q_a[0]_PORT_A_address, Z1_q_a[0]_clock_0, , , );
Z1_q_a[0]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[0]_PORT_A_data_out = MEMORY(, , Z1_q_a[0]_PORT_A_address_reg, , , , , , Z1_q_a[0]_clock_0, , , , , );
Z1_q_a[0]_PORT_A_data_out_reg = DFFE(Z1_q_a[0]_PORT_A_data_out, Z1_q_a[0]_clock_0, , , );
Z1_q_a[0] = Z1_q_a[0]_PORT_A_data_out_reg[0];
--Y1_q_a[0] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[0] at M4K_X33_Y4
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[0]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[0]_PORT_A_address_reg = DFFE(Y1_q_a[0]_PORT_A_address, Y1_q_a[0]_clock_0, , , );
Y1_q_a[0]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[0]_PORT_A_data_out = MEMORY(, , Y1_q_a[0]_PORT_A_address_reg, , , , , , Y1_q_a[0]_clock_0, , , , , );
Y1_q_a[0]_PORT_A_data_out_reg = DFFE(Y1_q_a[0]_PORT_A_data_out, Y1_q_a[0]_clock_0, , , );
Y1_q_a[0] = Y1_q_a[0]_PORT_A_data_out_reg[0];
--BB1_q_a[0] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[0] at M4K_X33_Y3
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[0]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[0]_PORT_A_address_reg = DFFE(BB1_q_a[0]_PORT_A_address, BB1_q_a[0]_clock_0, , , );
BB1_q_a[0]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[0]_PORT_A_data_out = MEMORY(, , BB1_q_a[0]_PORT_A_address_reg, , , , , , BB1_q_a[0]_clock_0, , , , , );
BB1_q_a[0]_PORT_A_data_out_reg = DFFE(BB1_q_a[0]_PORT_A_data_out, BB1_q_a[0]_clock_0, , , );
BB1_q_a[0] = BB1_q_a[0]_PORT_A_data_out_reg[0];
--H1L1 is mux4_1:inst7|cout[0]~152 at LC_X35_Y12_N2
--operation mode is normal
H1L1 = addr1 & addr0 # !addr1 & (addr0 & Y1_q_a[0] # !addr0 & (BB1_q_a[0]));
--AB1_q_a[0] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[0] at M4K_X19_Y7
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[0]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[0]_PORT_A_address_reg = DFFE(AB1_q_a[0]_PORT_A_address, AB1_q_a[0]_clock_0, , , );
AB1_q_a[0]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[0]_PORT_A_data_out = MEMORY(, , AB1_q_a[0]_PORT_A_address_reg, , , , , , AB1_q_a[0]_clock_0, , , , , );
AB1_q_a[0]_PORT_A_data_out_reg = DFFE(AB1_q_a[0]_PORT_A_data_out, AB1_q_a[0]_clock_0, , , );
AB1_q_a[0] = AB1_q_a[0]_PORT_A_data_out_reg[0];
--H1L2 is mux4_1:inst7|cout[0]~153 at LC_X21_Y9_N2
--operation mode is normal
H1L2 = addr1 & (H1L1 & (AB1_q_a[0]) # !H1L1 & Z1_q_a[0]) # !addr1 & (H1L1);
--CB1_q_a[9] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[9] at M4K_X33_Y24
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[9]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[9]_PORT_A_address_reg = DFFE(CB1_q_a[9]_PORT_A_address, CB1_q_a[9]_clock_0, , , );
CB1_q_a[9]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[9]_PORT_A_data_out = MEMORY(, , CB1_q_a[9]_PORT_A_address_reg, , , , , , CB1_q_a[9]_clock_0, , , , , );
CB1_q_a[9]_PORT_A_data_out_reg = DFFE(CB1_q_a[9]_PORT_A_data_out, CB1_q_a[9]_clock_0, , , );
CB1_q_a[9] = CB1_q_a[9]_PORT_A_data_out_reg[0];
--CB1_q_a[8] is cos_rom:inst38|altsyncram:altsyncram_component|altsyncram_2gr:auto_generated|q_a[8] at M4K_X19_Y24
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
CB1_q_a[8]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], J1_temp[8], J1_temp[9], J1_temp[10], J1_temp[11]);
CB1_q_a[8]_PORT_A_address_reg = DFFE(CB1_q_a[8]_PORT_A_address, CB1_q_a[8]_clock_0, , , );
CB1_q_a[8]_clock_0 = GLOBAL(Q1_clkout);
CB1_q_a[8]_PORT_A_data_out = MEMORY(, , CB1_q_a[8]_PORT_A_address_reg, , , , , , CB1_q_a[8]_clock_0, , , , , );
CB1_q_a[8]_PORT_A_data_out_reg = DFFE(CB1_q_a[8]_PORT_A_data_out, CB1_q_a[8]_clock_0, , , );
CB1_q_a[8] = CB1_q_a[8]_PORT_A_data_out_reg[0];
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