📄 dds.fit.eqn
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--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[8]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[8]_PORT_A_address_reg = DFFE(BB1_q_a[8]_PORT_A_address, BB1_q_a[8]_clock_0, , , );
BB1_q_a[8]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[8]_PORT_A_data_out = MEMORY(, , BB1_q_a[8]_PORT_A_address_reg, , , , , , BB1_q_a[8]_clock_0, , , , , );
BB1_q_a[8]_PORT_A_data_out_reg = DFFE(BB1_q_a[8]_PORT_A_data_out, BB1_q_a[8]_clock_0, , , );
BB1_q_a[8] = BB1_q_a[8]_PORT_A_data_out_reg[0];
--H1L71 is mux4_1:inst7|cout[8]~136 at LC_X21_Y12_N9
--operation mode is normal
H1L71 = addr0 & (Y1_q_a[8] # addr1) # !addr0 & (BB1_q_a[8] & !addr1);
--AB1_q_a[8] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[8] at M4K_X19_Y4
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[8]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[8]_PORT_A_address_reg = DFFE(AB1_q_a[8]_PORT_A_address, AB1_q_a[8]_clock_0, , , );
AB1_q_a[8]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[8]_PORT_A_data_out = MEMORY(, , AB1_q_a[8]_PORT_A_address_reg, , , , , , AB1_q_a[8]_clock_0, , , , , );
AB1_q_a[8]_PORT_A_data_out_reg = DFFE(AB1_q_a[8]_PORT_A_data_out, AB1_q_a[8]_clock_0, , , );
AB1_q_a[8] = AB1_q_a[8]_PORT_A_data_out_reg[0];
--H1L81 is mux4_1:inst7|cout[8]~137 at LC_X21_Y12_N7
--operation mode is normal
H1L81 = addr1 & (H1L71 & (AB1_q_a[8]) # !H1L71 & Z1_q_a[8]) # !addr1 & (H1L71);
--Y1_q_a[7] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[7] at M4K_X19_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[7]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[7]_PORT_A_address_reg = DFFE(Y1_q_a[7]_PORT_A_address, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[7]_PORT_A_data_out = MEMORY(, , Y1_q_a[7]_PORT_A_address_reg, , , , , , Y1_q_a[7]_clock_0, , , , , );
Y1_q_a[7]_PORT_A_data_out_reg = DFFE(Y1_q_a[7]_PORT_A_data_out, Y1_q_a[7]_clock_0, , , );
Y1_q_a[7] = Y1_q_a[7]_PORT_A_data_out_reg[0];
--Z1_q_a[7] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[7] at M4K_X19_Y16
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[7]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[7]_PORT_A_address_reg = DFFE(Z1_q_a[7]_PORT_A_address, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[7]_PORT_A_data_out = MEMORY(, , Z1_q_a[7]_PORT_A_address_reg, , , , , , Z1_q_a[7]_clock_0, , , , , );
Z1_q_a[7]_PORT_A_data_out_reg = DFFE(Z1_q_a[7]_PORT_A_data_out, Z1_q_a[7]_clock_0, , , );
Z1_q_a[7] = Z1_q_a[7]_PORT_A_data_out_reg[0];
--BB1_q_a[7] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[7] at M4K_X19_Y17
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[7]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[7]_PORT_A_address_reg = DFFE(BB1_q_a[7]_PORT_A_address, BB1_q_a[7]_clock_0, , , );
BB1_q_a[7]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[7]_PORT_A_data_out = MEMORY(, , BB1_q_a[7]_PORT_A_address_reg, , , , , , BB1_q_a[7]_clock_0, , , , , );
BB1_q_a[7]_PORT_A_data_out_reg = DFFE(BB1_q_a[7]_PORT_A_data_out, BB1_q_a[7]_clock_0, , , );
BB1_q_a[7] = BB1_q_a[7]_PORT_A_data_out_reg[0];
--H1L51 is mux4_1:inst7|cout[7]~138 at LC_X21_Y12_N8
--operation mode is normal
H1L51 = addr0 & (addr1) # !addr0 & (addr1 & Z1_q_a[7] # !addr1 & (BB1_q_a[7]));
--AB1_q_a[7] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[7] at M4K_X19_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[7]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[7]_PORT_A_address_reg = DFFE(AB1_q_a[7]_PORT_A_address, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[7]_PORT_A_data_out = MEMORY(, , AB1_q_a[7]_PORT_A_address_reg, , , , , , AB1_q_a[7]_clock_0, , , , , );
AB1_q_a[7]_PORT_A_data_out_reg = DFFE(AB1_q_a[7]_PORT_A_data_out, AB1_q_a[7]_clock_0, , , );
AB1_q_a[7] = AB1_q_a[7]_PORT_A_data_out_reg[0];
--H1L61 is mux4_1:inst7|cout[7]~139 at LC_X21_Y12_N4
--operation mode is normal
H1L61 = H1L51 & (AB1_q_a[7] # !addr0) # !H1L51 & (addr0 & Y1_q_a[7]);
--Z1_q_a[6] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[6] at M4K_X19_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[6]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[6]_PORT_A_address_reg = DFFE(Z1_q_a[6]_PORT_A_address, Z1_q_a[6]_clock_0, , , );
Z1_q_a[6]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[6]_PORT_A_data_out = MEMORY(, , Z1_q_a[6]_PORT_A_address_reg, , , , , , Z1_q_a[6]_clock_0, , , , , );
Z1_q_a[6]_PORT_A_data_out_reg = DFFE(Z1_q_a[6]_PORT_A_data_out, Z1_q_a[6]_clock_0, , , );
Z1_q_a[6] = Z1_q_a[6]_PORT_A_data_out_reg[0];
--Y1_q_a[6] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[6] at M4K_X19_Y2
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[6]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[6]_PORT_A_address_reg = DFFE(Y1_q_a[6]_PORT_A_address, Y1_q_a[6]_clock_0, , , );
Y1_q_a[6]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[6]_PORT_A_data_out = MEMORY(, , Y1_q_a[6]_PORT_A_address_reg, , , , , , Y1_q_a[6]_clock_0, , , , , );
Y1_q_a[6]_PORT_A_data_out_reg = DFFE(Y1_q_a[6]_PORT_A_data_out, Y1_q_a[6]_clock_0, , , );
Y1_q_a[6] = Y1_q_a[6]_PORT_A_data_out_reg[0];
--BB1_q_a[6] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[6] at M4K_X19_Y3
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[6]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[6]_PORT_A_address_reg = DFFE(BB1_q_a[6]_PORT_A_address, BB1_q_a[6]_clock_0, , , );
BB1_q_a[6]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[6]_PORT_A_data_out = MEMORY(, , BB1_q_a[6]_PORT_A_address_reg, , , , , , BB1_q_a[6]_clock_0, , , , , );
BB1_q_a[6]_PORT_A_data_out_reg = DFFE(BB1_q_a[6]_PORT_A_data_out, BB1_q_a[6]_clock_0, , , );
BB1_q_a[6] = BB1_q_a[6]_PORT_A_data_out_reg[0];
--H1L31 is mux4_1:inst7|cout[6]~140 at LC_X21_Y12_N1
--operation mode is normal
H1L31 = addr0 & (addr1 # Y1_q_a[6]) # !addr0 & !addr1 & (BB1_q_a[6]);
--AB1_q_a[6] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[6] at M4K_X19_Y9
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[6]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[6]_PORT_A_address_reg = DFFE(AB1_q_a[6]_PORT_A_address, AB1_q_a[6]_clock_0, , , );
AB1_q_a[6]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[6]_PORT_A_data_out = MEMORY(, , AB1_q_a[6]_PORT_A_address_reg, , , , , , AB1_q_a[6]_clock_0, , , , , );
AB1_q_a[6]_PORT_A_data_out_reg = DFFE(AB1_q_a[6]_PORT_A_data_out, AB1_q_a[6]_clock_0, , , );
AB1_q_a[6] = AB1_q_a[6]_PORT_A_data_out_reg[0];
--H1L41 is mux4_1:inst7|cout[6]~141 at LC_X21_Y9_N4
--operation mode is normal
H1L41 = addr1 & (H1L31 & (AB1_q_a[6]) # !H1L31 & Z1_q_a[6]) # !addr1 & H1L31;
--Y1_q_a[5] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[5] at M4K_X33_Y17
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[5]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[5]_PORT_A_address_reg = DFFE(Y1_q_a[5]_PORT_A_address, Y1_q_a[5]_clock_0, , , );
Y1_q_a[5]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[5]_PORT_A_data_out = MEMORY(, , Y1_q_a[5]_PORT_A_address_reg, , , , , , Y1_q_a[5]_clock_0, , , , , );
Y1_q_a[5]_PORT_A_data_out_reg = DFFE(Y1_q_a[5]_PORT_A_data_out, Y1_q_a[5]_clock_0, , , );
Y1_q_a[5] = Y1_q_a[5]_PORT_A_data_out_reg[0];
--Z1_q_a[5] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[5] at M4K_X33_Y20
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[5]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[5]_PORT_A_address_reg = DFFE(Z1_q_a[5]_PORT_A_address, Z1_q_a[5]_clock_0, , , );
Z1_q_a[5]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[5]_PORT_A_data_out = MEMORY(, , Z1_q_a[5]_PORT_A_address_reg, , , , , , Z1_q_a[5]_clock_0, , , , , );
Z1_q_a[5]_PORT_A_data_out_reg = DFFE(Z1_q_a[5]_PORT_A_data_out, Z1_q_a[5]_clock_0, , , );
Z1_q_a[5] = Z1_q_a[5]_PORT_A_data_out_reg[0];
--BB1_q_a[5] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[5] at M4K_X33_Y7
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[5]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[5]_PORT_A_address_reg = DFFE(BB1_q_a[5]_PORT_A_address, BB1_q_a[5]_clock_0, , , );
BB1_q_a[5]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[5]_PORT_A_data_out = MEMORY(, , BB1_q_a[5]_PORT_A_address_reg, , , , , , BB1_q_a[5]_clock_0, , , , , );
BB1_q_a[5]_PORT_A_data_out_reg = DFFE(BB1_q_a[5]_PORT_A_data_out, BB1_q_a[5]_clock_0, , , );
BB1_q_a[5] = BB1_q_a[5]_PORT_A_data_out_reg[0];
--H1L11 is mux4_1:inst7|cout[5]~142 at LC_X35_Y12_N8
--operation mode is normal
H1L11 = addr1 & (addr0 # Z1_q_a[5]) # !addr1 & !addr0 & BB1_q_a[5];
--AB1_q_a[5] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[5] at M4K_X33_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[5]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[5]_PORT_A_address_reg = DFFE(AB1_q_a[5]_PORT_A_address, AB1_q_a[5]_clock_0, , , );
AB1_q_a[5]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[5]_PORT_A_data_out = MEMORY(, , AB1_q_a[5]_PORT_A_address_reg, , , , , , AB1_q_a[5]_clock_0, , , , , );
AB1_q_a[5]_PORT_A_data_out_reg = DFFE(AB1_q_a[5]_PORT_A_data_out, AB1_q_a[5]_clock_0, , , );
AB1_q_a[5] = AB1_q_a[5]_PORT_A_data_out_reg[0];
--H1L21 is mux4_1:inst7|cout[5]~143 at LC_X35_Y12_N5
--operation mode is normal
H1L21 = addr0 & (H1L11 & (AB1_q_a[5]) # !H1L11 & Y1_q_a[5]) # !addr0 & (H1L11);
--Z1_q_a[4] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[4] at M4K_X33_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[4]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[4]_PORT_A_address_reg = DFFE(Z1_q_a[4]_PORT_A_address, Z1_q_a[4]_clock_0, , , );
Z1_q_a[4]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[4]_PORT_A_data_out = MEMORY(, , Z1_q_a[4]_PORT_A_address_reg, , , , , , Z1_q_a[4]_clock_0, , , , , );
Z1_q_a[4]_PORT_A_data_out_reg = DFFE(Z1_q_a[4]_PORT_A_data_out, Z1_q_a[4]_clock_0, , , );
Z1_q_a[4] = Z1_q_a[4]_PORT_A_data_out_reg[0];
--Y1_q_a[4] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[4] at M4K_X33_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[4]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[4]_PORT_A_address_reg = DFFE(Y1_q_a[4]_PORT_A_address, Y1_q_a[4]_clock_0, , , );
Y1_q_a[4]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[4]_PORT_A_data_out = MEMORY(, , Y1_q_a[4]_PORT_A_address_reg, , , , , , Y1_q_a[4]_clock_0, , , , , );
Y1_q_a[4]_PORT_A_data_out_reg = DFFE(Y1_q_a[4]_PORT_A_data_out, Y1_q_a[4]_clock_0, , , );
Y1_q_a[4] = Y1_q_a[4]_PORT_A_data_out_reg[0];
--BB1_q_a[4] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[4] at M4K_X33_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[4]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[4]_PORT_A_address_reg = DFFE(BB1_q_a[4]_PORT_A_address, BB1_q_a[4]_clock_0, , , );
BB1_q_a[4]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[4]_PORT_A_data_out = MEMORY(, , BB1_q_a[4]_PORT_A_address_reg, , , , , , BB1_q_a[4]_clock_0, , , , , );
BB1_q_a[4]_PORT_A_data_out_reg = DFFE(BB1_q_a[4]_PORT_A_data_out, BB1_q_a[4]_clock_0, , , );
BB1_q_a[4] = BB1_q_a[4]_PORT_A_data_out_reg[0];
--H1L9 is mux4_1:inst7|cout[4]~144 at LC_X35_Y12_N4
--operation mode is normal
H1L9 = addr1 & addr0 # !addr1 & (addr0 & Y1_q_a[4] # !addr0 & (BB1_q_a[4]));
--AB1_q_a[4] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[4] at M4K_X33_Y16
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[4]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[4]_PORT_A_address_reg = DFFE(AB1_q_a[4]_PORT_A_address, AB1_q_a[4]_clock_0, , , );
AB1_q_a[4]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[4]_PORT_A_data_out = MEMORY(, , AB1_q_a[4]_PORT_A_address_reg, , , , , , AB1_q_a[4]_clock_0, , , , , );
AB1_q_a[4]_PORT_A_data_out_reg = DFFE(AB1_q_a[4]_PORT_A_data_out, AB1_q_a[4]_clock_0, , , );
AB1_q_a[4] = AB1_q_a[4]_PORT_A_data_out_reg[0];
--H1L01 is mux4_1:inst7|cout[4]~145 at LC_X35_Y12_N1
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