dds.fit.eqn

在quartus软件下用VHDL语言实现DDS

--T1L22 is xianshi:inst6|mux8_1:inst|res3~201 at LC_X42_Y13_N5
--operation mode is normal

S1_out3[3]_qfbk = S1_out3[3];
T1L22 = T1L81 & (T1L12 & (S1_out3[3]_qfbk) # !T1L12 & D1L6) # !T1L81 & (T1L12);

--S1_out3[3] is cef:inst3|lock:inst5|out3[3] at LC_X42_Y13_N5
--operation mode is normal

S1_out3[3] = DFFEAS(T1L22, GLOBAL(Q4_clkout), VCC, , , R4_temp[3], , , VCC);


--T1L32 is xianshi:inst6|mux8_1:inst|res3~202 at LC_X42_Y14_N7
--operation mode is normal

T1L32 = T1L22 & (U1_m8t[2] # !Q3_temp[0]);


--S1_out0[0] is cef:inst3|lock:inst5|out0[0] at LC_X41_Y15_N2
--operation mode is normal

S1_out0[0]_lut_out = GND;
S1_out0[0] = DFFEAS(S1_out0[0]_lut_out, GLOBAL(Q4_clkout), VCC, , , R1_temp[0], , , VCC);


--T1L1 is xianshi:inst6|mux8_1:inst|res0~65 at LC_X41_Y14_N7
--operation mode is normal

S1_out1[0]_qfbk = S1_out1[0];
T1L1 = Q3_temp[0] & (U1_m8t[1] # S1_out1[0]_qfbk) # !Q3_temp[0] & !U1_m8t[1] & (S1_out0[0]);

--S1_out1[0] is cef:inst3|lock:inst5|out1[0] at LC_X41_Y14_N7
--operation mode is normal

S1_out1[0] = DFFEAS(T1L1, GLOBAL(Q4_clkout), VCC, , , R2_temp[0], , , VCC);


--S1_out3[0] is cef:inst3|lock:inst5|out3[0] at LC_X41_Y14_N5
--operation mode is normal

S1_out3[0]_lut_out = GND;
S1_out3[0] = DFFEAS(S1_out3[0]_lut_out, GLOBAL(Q4_clkout), VCC, , , R4_temp[0], , , VCC);


--T1L2 is xianshi:inst6|mux8_1:inst|res0~66 at LC_X41_Y14_N3
--operation mode is normal

S1_out2[0]_qfbk = S1_out2[0];
T1L2 = T1L1 & (S1_out3[0] # !U1_m8t[1]) # !T1L1 & U1_m8t[1] & S1_out2[0]_qfbk;

--S1_out2[0] is cef:inst3|lock:inst5|out2[0] at LC_X41_Y14_N3
--operation mode is normal

S1_out2[0] = DFFEAS(T1L2, GLOBAL(Q4_clkout), VCC, , , R3_temp[0], , , VCC);


--D1_temp_ph[0] is counter:inst2|temp_ph[0] at LC_X23_Y14_N2
--operation mode is normal

D1_temp_ph[0]_lut_out = !D1_temp_ph[0];
D1_temp_ph[0] = DFFEAS(D1_temp_ph[0]_lut_out, GLOBAL(C1_inst8), !C1_inst, , , , , , );


--D1L11 is counter:inst2|dis_ljten[0]~49 at LC_X24_Y14_N3
--operation mode is normal

D1L11 = D1_temp_lj[3] & (D1_temp_lj[1] # D1_temp_lj[2]);


--D1_temp_lj[0] is counter:inst2|temp_lj[0] at LC_X25_Y14_N3
--operation mode is normal

D1_temp_lj[0]_lut_out = !D1_temp_lj[0];
D1_temp_lj[0] = DFFEAS(D1_temp_lj[0]_lut_out, C1_inst4, !C1_inst, , , , , , );


--T1L3 is xianshi:inst6|mux8_1:inst|res0~67 at LC_X25_Y14_N0
--operation mode is normal

T1L3 = Q3_temp[0] & (D1L11 # U1_m8t[1]) # !Q3_temp[0] & (!U1_m8t[1] & D1_temp_lj[0]);


--T1L4 is xianshi:inst6|mux8_1:inst|res0~68 at LC_X25_Y14_N2
--operation mode is normal

T1L4 = U1_m8t[1] & (T1L3 & D1L21 # !T1L3 & (D1_temp_ph[0])) # !U1_m8t[1] & (T1L3);


--T1L5 is xianshi:inst6|mux8_1:inst|res0~69 at LC_X25_Y14_N6
--operation mode is normal

T1L5 = U1_m8t[2] & (T1L2) # !U1_m8t[2] & T1L4;


--V1L2 is xianshi:inst6|7447:inst2|81~48 at LC_X42_Y14_N6
--operation mode is normal

V1L2 = T1L61 & (!T1L5) # !T1L61 & !T1L01 & !T1L32 & T1L5;


--T1L11 is xianshi:inst6|mux8_1:inst|res1~155 at LC_X29_Y14_N7
--operation mode is normal

T1L11 = T1L9 & T1L22 & (U1_m8t[2] # !Q3_temp[0]);


--V1_81 is xianshi:inst6|7447:inst2|81 at LC_X29_Y14_N2
--operation mode is normal

V1_81 = T1L11 # V1L2;


--V1L3 is xianshi:inst6|7447:inst2|82~212 at LC_X29_Y14_N1
--operation mode is normal

V1L3 = T1L11 # T1L61 & (T1L01 $ T1L5);


--V1_83 is xianshi:inst6|7447:inst2|83 at LC_X42_Y14_N8
--operation mode is normal

V1_83 = T1L61 & (T1L22) # !T1L61 & T1L01 & (!T1L5);


--V1L5 is xianshi:inst6|7447:inst2|84~172 at LC_X42_Y15_N2
--operation mode is normal

V1L5 = T1L61 & (T1L01 $ (!T1L5)) # !T1L61 & !T1L01 & (T1L5);


--V1_85 is xianshi:inst6|7447:inst2|85 at LC_X42_Y15_N4
--operation mode is normal

V1_85 = T1L5 # T1L61 & !T1L01;


--V1L7 is xianshi:inst6|7447:inst2|86~44 at LC_X42_Y14_N4
--operation mode is normal

V1L7 = T1L01 & (T1L5 # !T1L61) # !T1L01 & !T1L61 & !T1L32 & T1L5;


--V1_87 is xianshi:inst6|7447:inst2|87 at LC_X42_Y14_N5
--operation mode is normal

V1_87 = T1L01 & T1L61 & (T1L5) # !T1L01 & !T1L61 & !T1L32;


--W1L4 is xianshi:inst6|74138:inst3|15~105 at LC_X43_Y14_N7
--operation mode is normal

W1L4 = Q3_temp[0] & !U1_m8t[1] & !U1_m8t[2];


--W1L5 is xianshi:inst6|74138:inst3|15~106 at LC_X43_Y14_N0
--operation mode is normal

W1L5 = Q3_temp[0] & U1_m8t[1] & !U1_m8t[2];


--W1L6 is xianshi:inst6|74138:inst3|15~107 at LC_X43_Y14_N4
--operation mode is normal

W1L6 = !Q3_temp[0] & !U1_m8t[1] & U1_m8t[2];


--W1L7 is xianshi:inst6|74138:inst3|15~108 at LC_X43_Y14_N3
--operation mode is normal

W1L7 = Q3_temp[0] & !U1_m8t[1] & U1_m8t[2];


--W1L8 is xianshi:inst6|74138:inst3|15~109 at LC_X43_Y14_N2
--operation mode is normal

W1L8 = !Q3_temp[0] & U1_m8t[1] & U1_m8t[2];


--W1L9 is xianshi:inst6|74138:inst3|15~110 at LC_X43_Y14_N8
--operation mode is normal

W1L9 = Q3_temp[0] & U1_m8t[1] & U1_m8t[2];


--Q1_clkout is fp:inst|fpq:inst|clkout at LC_X8_Y13_N0
--operation mode is normal

Q1_clkout_lut_out = Q1_temp[5] & (Q1_temp[0] & !Q1L91);
Q1_clkout = DFFEAS(Q1_clkout_lut_out, GLOBAL(clk), VCC, , , , , , );


--Y1_q_a[9] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[9] at M4K_X19_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[9]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[9]_PORT_A_address_reg = DFFE(Y1_q_a[9]_PORT_A_address, Y1_q_a[9]_clock_0, , , );
Y1_q_a[9]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[9]_PORT_A_data_out = MEMORY(, , Y1_q_a[9]_PORT_A_address_reg, , , , , , Y1_q_a[9]_clock_0, , , , , );
Y1_q_a[9]_PORT_A_data_out_reg = DFFE(Y1_q_a[9]_PORT_A_data_out, Y1_q_a[9]_clock_0, , , );
Y1_q_a[9] = Y1_q_a[9]_PORT_A_data_out_reg[0];


--Z1_q_a[9] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[9] at M4K_X19_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[9]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[9]_PORT_A_address_reg = DFFE(Z1_q_a[9]_PORT_A_address, Z1_q_a[9]_clock_0, , , );
Z1_q_a[9]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[9]_PORT_A_data_out = MEMORY(, , Z1_q_a[9]_PORT_A_address_reg, , , , , , Z1_q_a[9]_clock_0, , , , , );
Z1_q_a[9]_PORT_A_data_out_reg = DFFE(Z1_q_a[9]_PORT_A_data_out, Z1_q_a[9]_clock_0, , , );
Z1_q_a[9] = Z1_q_a[9]_PORT_A_data_out_reg[0];


--BB1_q_a[9] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[9] at M4K_X19_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
BB1_q_a[9]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
BB1_q_a[9]_PORT_A_address_reg = DFFE(BB1_q_a[9]_PORT_A_address, BB1_q_a[9]_clock_0, , , );
BB1_q_a[9]_clock_0 = GLOBAL(Q1_clkout);
BB1_q_a[9]_PORT_A_data_out = MEMORY(, , BB1_q_a[9]_PORT_A_address_reg, , , , , , BB1_q_a[9]_clock_0, , , , , );
BB1_q_a[9]_PORT_A_data_out_reg = DFFE(BB1_q_a[9]_PORT_A_data_out, BB1_q_a[9]_clock_0, , , );
BB1_q_a[9] = BB1_q_a[9]_PORT_A_data_out_reg[0];


--H1L91 is mux4_1:inst7|cout[9]~134 at LC_X21_Y12_N3
--operation mode is normal

H1L91 = addr1 & (Z1_q_a[9] # addr0) # !addr1 & (!addr0 & BB1_q_a[9]);


--AB1_q_a[9] is juxing_rom:inst29|altsyncram:altsyncram_component|altsyncram_ifs:auto_generated|q_a[9] at M4K_X19_Y19
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
AB1_q_a[9]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
AB1_q_a[9]_PORT_A_address_reg = DFFE(AB1_q_a[9]_PORT_A_address, AB1_q_a[9]_clock_0, , , );
AB1_q_a[9]_clock_0 = GLOBAL(Q1_clkout);
AB1_q_a[9]_PORT_A_data_out = MEMORY(, , AB1_q_a[9]_PORT_A_address_reg, , , , , , AB1_q_a[9]_clock_0, , , , , );
AB1_q_a[9]_PORT_A_data_out_reg = DFFE(AB1_q_a[9]_PORT_A_data_out, AB1_q_a[9]_clock_0, , , );
AB1_q_a[9] = AB1_q_a[9]_PORT_A_data_out_reg[0];


--H1L02 is mux4_1:inst7|cout[9]~135 at LC_X21_Y12_N2
--operation mode is normal

H1L02 = H1L91 & (AB1_q_a[9] # !addr0) # !H1L91 & Y1_q_a[9] & addr0;


--Z1_q_a[8] is juchi_rom:inst28|altsyncram:altsyncram_component|altsyncram_c3s:auto_generated|q_a[8] at M4K_X33_Y19
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Z1_q_a[8]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Z1_q_a[8]_PORT_A_address_reg = DFFE(Z1_q_a[8]_PORT_A_address, Z1_q_a[8]_clock_0, , , );
Z1_q_a[8]_clock_0 = GLOBAL(Q1_clkout);
Z1_q_a[8]_PORT_A_data_out = MEMORY(, , Z1_q_a[8]_PORT_A_address_reg, , , , , , Z1_q_a[8]_clock_0, , , , , );
Z1_q_a[8]_PORT_A_data_out_reg = DFFE(Z1_q_a[8]_PORT_A_data_out, Z1_q_a[8]_clock_0, , , );
Z1_q_a[8] = Z1_q_a[8]_PORT_A_data_out_reg[0];


--Y1_q_a[8] is sanjiao_rom:inst27|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|q_a[8] at M4K_X19_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
Y1_q_a[8]_PORT_A_address = BUS(J1_temp[0], J1_temp[1], J1_temp[2], J1_temp[3], J1_temp[4], J1_temp[5], J1_temp[6], J1_temp[7], F1L1, F1L4, F1L7, F1L01);
Y1_q_a[8]_PORT_A_address_reg = DFFE(Y1_q_a[8]_PORT_A_address, Y1_q_a[8]_clock_0, , , );
Y1_q_a[8]_clock_0 = GLOBAL(Q1_clkout);
Y1_q_a[8]_PORT_A_data_out = MEMORY(, , Y1_q_a[8]_PORT_A_address_reg, , , , , , Y1_q_a[8]_clock_0, , , , , );
Y1_q_a[8]_PORT_A_data_out_reg = DFFE(Y1_q_a[8]_PORT_A_data_out, Y1_q_a[8]_clock_0, , , );
Y1_q_a[8] = Y1_q_a[8]_PORT_A_data_out_reg[0];


--BB1_q_a[8] is sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[8] at M4K_X19_Y20
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1