tbu.v

(2,1,9)卷积编解码器

`include "params.v"



module TBU (Reset, Clock1, Clock2, TB_EN, Init, Hold, InitState, 
  	      DecodedData, DataTB, AddressTB);

input Reset, Clock1, Clock2, Init, Hold;
input [`WD_STATE-1:0] InitState;
input TB_EN;

input [`WD_RAM_DATA-1:0] DataTB;
output [`WD_RAM_ADDRESS-`WD_FSM-1:0] AddressTB;

output DecodedData;

wire [`WD_STATE-1:0] OutStateTB;

   TRACEUNIT tb (Reset, Clock1, Clock2, TB_EN, InitState, Init, Hold, 
   		 DataTB, AddressTB, OutStateTB);
   
   assign DecodedData = OutStateTB [`WD_STATE-1];

endmodule



module TRACEUNIT (Reset, Clock1, Clock2, Enable, InitState, Init, Hold, 
  		    Survivor, AddressTB, OutState);


input Reset, Clock1, Clock2, Enable;
input [`WD_STATE-1:0] InitState;
input Init, Hold;
input [`WD_RAM_DATA-1:0] Survivor;

output [`WD_STATE-1:0] OutState;

output [`WD_RAM_ADDRESS-`WD_FSM-1:0] AddressTB;

reg [`WD_STATE-1:0] CurrentState;
reg [`WD_STATE-1:0] NextState;
reg [`WD_STATE-1:0] OutState;

wire SurvivorBit;

    always @(negedge Clock1 or negedge Reset)
    begin
       if (~Reset) begin
          CurrentState <=0; OutState <=0;
       end
       else if (Enable)
         begin 
            if (Init) CurrentState <= InitState;
               else CurrentState <= NextState;
          
            if (Hold) OutState <= NextState;
         end
    end

    assign AddressTB = CurrentState [`WD_STATE-1:`WD_STATE-5];

    always @(negedge Clock2 or negedge Reset)
    begin
      if (~Reset) NextState <= 0;
       else 
         if (Enable) NextState <= {CurrentState [`WD_STATE-2:0],SurvivorBit};
    end

    assign SurvivorBit = 
          (Clock1 && Clock2 && ~Init) ? Survivor [CurrentState [2:0]]:'bz;
   
endmodule